📄 fry.rpt
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Total single-pin Clock Enables required: 0
Total single-pin Output Enables required: 0
Synthesized logic cells: 8/ 576 ( 1%)
Logic Cell and Embedded Cell Counts
Column: 01 02 03 04 05 06 07 08 09 10 11 12 EA 13 14 15 16 17 18 19 20 21 22 23 24 Total(LC/EC)
A: 8 1 6 8 4 8 8 1 7 8 8 0 0 8 1 8 2 8 8 7 8 8 0 1 8 134/0
B: 0 1 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3/0
C: 1 1 1 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5/0
Total: 9 3 8 9 5 9 8 1 7 8 8 0 0 8 1 8 2 8 8 7 8 8 0 1 8 142/0
Device-Specific Information: d:\edaplay\digital\test20\frequency\fry.rpt
fry
** INPUTS **
Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
1 - - - -- INPUT 0 0 0 2 clk
43 - - - -- INPUT 0 0 0 4 fryin
54 - - - 21 INPUT 0 0 0 1 p10
58 - - C -- INPUT 0 0 0 1 p11
59 - - C -- INPUT 0 0 0 1 p12
60 - - C -- INPUT 0 0 0 1 p13
61 - - C -- INPUT 0 0 0 1 p14
62 - - C -- INPUT 0 0 0 1 p15
64 - - B -- INPUT 0 0 0 1 p16
65 - - B -- INPUT 0 0 0 1 p17
27 - - C -- INPUT 0 0 0 7 sel0
28 - - C -- INPUT 0 0 0 7 sel1
29 - - C -- INPUT 0 0 0 7 sel2
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: d:\edaplay\digital\test20\frequency\fry.rpt
fry
** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
66 - - B -- OUTPUT 0 1 0 0 A
67 - - B -- OUTPUT 0 1 0 0 B
70 - - A -- OUTPUT 0 1 0 0 C
71 - - A -- OUTPUT 0 1 0 0 D
5 - - - 05 OUTPUT 0 1 0 0 d0
6 - - - 04 OUTPUT 0 1 0 0 d1
7 - - - 03 OUTPUT 0 1 0 0 d2
8 - - - 03 OUTPUT 0 1 0 0 d3
9 - - - 02 OUTPUT 0 1 0 0 d4
10 - - - 01 OUTPUT 0 1 0 0 d5
11 - - - 01 OUTPUT 0 1 0 0 d6
16 - - A -- OUTPUT 0 1 0 0 d7
72 - - A -- OUTPUT 0 1 0 0 E
73 - - A -- OUTPUT 0 0 0 0 F
78 - - - 24 OUTPUT 0 0 0 0 G
79 - - - 24 OUTPUT 0 0 0 0 H
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: d:\edaplay\digital\test20\frequency\fry.rpt
fry
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 8 - A 18 AND2 0 2 0 1 |CNT10:1|LPM_ADD_SUB:82|addcore:adder|:59
- 7 - A 18 OR2 0 4 0 1 |CNT10:1|LPM_ADD_SUB:82|addcore:adder|:77
- 2 - A 18 DFFE 0 5 0 4 |CNT10:1|cqi3 (|CNT10:1|:9)
- 3 - A 18 DFFE 0 5 0 4 |CNT10:1|cqi2 (|CNT10:1|:10)
- 5 - A 18 DFFE 0 5 0 5 |CNT10:1|cqi1 (|CNT10:1|:11)
- 1 - A 18 DFFE 0 4 0 6 |CNT10:1|cqi0 (|CNT10:1|:12)
- 6 - A 18 OR2 0 4 0 4 |CNT10:1|:48
- 4 - A 18 AND2 0 4 0 4 |CNT10:1|:194
- 7 - A 15 AND2 0 2 0 1 |CNT10:3|LPM_ADD_SUB:82|addcore:adder|:59
- 6 - A 15 OR2 0 4 0 1 |CNT10:3|LPM_ADD_SUB:82|addcore:adder|:77
- 8 - A 15 DFFE 0 5 0 4 |CNT10:3|cqi3 (|CNT10:3|:9)
- 1 - A 15 DFFE 0 5 0 4 |CNT10:3|cqi2 (|CNT10:3|:10)
- 4 - A 15 DFFE 0 5 0 5 |CNT10:3|cqi1 (|CNT10:3|:11)
- 3 - A 15 DFFE 0 4 0 6 |CNT10:3|cqi0 (|CNT10:3|:12)
- 5 - A 15 OR2 0 4 0 4 |CNT10:3|:48
- 2 - A 15 AND2 0 4 0 4 |CNT10:3|:194
- 8 - A 21 AND2 0 2 0 1 |CNT10:4|LPM_ADD_SUB:82|addcore:adder|:59
- 7 - A 21 OR2 0 4 0 1 |CNT10:4|LPM_ADD_SUB:82|addcore:adder|:77
- 5 - A 21 DFFE 0 5 0 4 |CNT10:4|cqi3 (|CNT10:4|:9)
- 1 - A 21 DFFE 0 5 0 4 |CNT10:4|cqi2 (|CNT10:4|:10)
- 2 - A 21 DFFE 0 5 0 5 |CNT10:4|cqi1 (|CNT10:4|:11)
- 3 - A 21 DFFE 0 4 0 6 |CNT10:4|cqi0 (|CNT10:4|:12)
- 6 - A 21 OR2 0 4 0 4 |CNT10:4|:48
- 4 - A 21 AND2 0 4 0 4 |CNT10:4|:194
- 8 - A 11 AND2 0 2 0 1 |CNT10:5|LPM_ADD_SUB:82|addcore:adder|:59
- 6 - A 11 OR2 0 4 0 1 |CNT10:5|LPM_ADD_SUB:82|addcore:adder|:77
- 4 - A 11 DFFE 0 5 0 4 |CNT10:5|cqi3 (|CNT10:5|:9)
- 1 - A 11 DFFE 0 5 0 4 |CNT10:5|cqi2 (|CNT10:5|:10)
- 2 - A 11 DFFE 0 5 0 5 |CNT10:5|cqi1 (|CNT10:5|:11)
- 3 - A 11 DFFE 0 4 0 6 |CNT10:5|cqi0 (|CNT10:5|:12)
- 7 - A 11 OR2 0 4 0 4 |CNT10:5|:48
- 5 - A 11 AND2 0 4 0 4 |CNT10:5|:194
- 8 - A 01 AND2 0 2 0 1 |CNT10:6|LPM_ADD_SUB:82|addcore:adder|:59
- 6 - A 01 OR2 0 4 0 1 |CNT10:6|LPM_ADD_SUB:82|addcore:adder|:77
- 4 - A 01 DFFE 0 5 0 4 |CNT10:6|cqi3 (|CNT10:6|:9)
- 1 - A 01 DFFE 0 5 0 4 |CNT10:6|cqi2 (|CNT10:6|:10)
- 2 - A 01 DFFE 0 5 0 5 |CNT10:6|cqi1 (|CNT10:6|:11)
- 3 - A 01 DFFE 0 4 0 6 |CNT10:6|cqi0 (|CNT10:6|:12)
- 7 - A 01 OR2 0 4 0 4 |CNT10:6|:48
- 5 - A 01 AND2 0 4 0 4 |CNT10:6|:194
- 8 - A 10 AND2 0 2 0 1 |CNT10:7|LPM_ADD_SUB:82|addcore:adder|:59
- 7 - A 10 OR2 0 4 0 1 |CNT10:7|LPM_ADD_SUB:82|addcore:adder|:77
- 4 - A 10 DFFE 0 5 0 4 |CNT10:7|cqi3 (|CNT10:7|:9)
- 3 - A 10 DFFE 0 5 0 4 |CNT10:7|cqi2 (|CNT10:7|:10)
- 5 - A 10 DFFE 0 5 0 5 |CNT10:7|cqi1 (|CNT10:7|:11)
- 2 - A 10 DFFE 0 4 0 6 |CNT10:7|cqi0 (|CNT10:7|:12)
- 6 - A 10 OR2 0 4 0 4 |CNT10:7|:48
- 1 - A 10 AND2 0 4 0 4 |CNT10:7|:194
- 5 - A 06 AND2 0 2 0 1 |CNT10:8|LPM_ADD_SUB:82|addcore:adder|:59
- 2 - A 06 OR2 0 4 0 1 |CNT10:8|LPM_ADD_SUB:82|addcore:adder|:77
- 4 - A 06 DFFE 0 5 0 2 |CNT10:8|cqi3 (|CNT10:8|:9)
- 6 - A 06 DFFE 0 5 0 2 |CNT10:8|cqi2 (|CNT10:8|:10)
- 7 - A 06 DFFE 0 5 0 3 |CNT10:8|cqi1 (|CNT10:8|:11)
- 8 - A 06 DFFE 0 4 0 5 |CNT10:8|cqi0 (|CNT10:8|:12)
- 3 - A 06 OR2 0 4 0 4 |CNT10:8|:48
- 8 - A 17 AND2 0 2 0 1 |CNT10:9|LPM_ADD_SUB:82|addcore:adder|:59
- 6 - A 17 OR2 0 4 0 1 |CNT10:9|LPM_ADD_SUB:82|addcore:adder|:77
- 3 - A 17 DFFE 1 4 0 4 |CNT10:9|cqi3 (|CNT10:9|:9)
- 4 - A 17 DFFE 1 4 0 4 |CNT10:9|cqi2 (|CNT10:9|:10)
- 7 - A 17 DFFE 1 4 0 5 |CNT10:9|cqi1 (|CNT10:9|:11)
- 2 - A 17 DFFE 1 3 0 6 |CNT10:9|cqi0 (|CNT10:9|:12)
- 5 - A 17 OR2 0 4 0 4 |CNT10:9|:48
- 1 - A 17 AND2 0 4 0 4 |CNT10:9|:194
- 3 - A 19 OR2 0 3 1 0 |DELED:65|:516
- 4 - A 13 AND2 0 3 1 0 |DELED:65|:551
- 5 - A 13 AND2 0 2 1 0 |DELED:65|:584
- 1 - A 13 AND2 0 2 1 0 |DELED:65|:617
- 3 - A 13 OR2 0 4 1 0 |DELED:65|:650
- 2 - C 06 LCELL s 1 0 1 0 d0~1
- 4 - B 03 LCELL s 1 0 1 0 d1~1
- 3 - C 04 LCELL s 1 0 1 0 d2~1
- 2 - C 03 LCELL s 1 0 1 0 d3~1
- 2 - C 01 LCELL s 1 0 1 0 d4~1
- 4 - C 02 LCELL s 1 0 1 0 d5~1
- 2 - B 02 LCELL s 1 0 1 0 d6~1
- 1 - B 05 LCELL s 1 0 1 0 d7~1
- 1 - A 06 DFFE 0 2 0 1 |REG32B:2|:40
- 3 - A 07 DFFE 0 2 0 2 |REG32B:2|:42
- 1 - A 08 DFFE 0 2 0 2 |REG32B:2|:44
- 2 - A 04 DFFE 0 2 0 2 |REG32B:2|:46
- 3 - A 04 DFFE 0 2 0 1 |REG32B:2|:48
- 1 - A 02 DFFE 0 2 0 1 |REG32B:2|:50
- 7 - A 07 DFFE 0 2 0 1 |REG32B:2|:52
- 4 - A 03 DFFE 0 2 0 1 |REG32B:2|:54
- 1 - A 04 DFFE 0 2 0 1 |REG32B:2|:56
- 6 - A 07 DFFE 0 2 0 1 |REG32B:2|:58
- 2 - A 05 DFFE 0 2 0 1 |REG32B:2|:60
- 3 - A 03 DFFE 0 2 0 1 |REG32B:2|:62
- 7 - A 04 DFFE 0 2 0 1 |REG32B:2|:64
- 2 - A 20 DFFE 0 2 0 1 |REG32B:2|:66
- 4 - A 05 DFFE 0 2 0 1 |REG32B:2|:68
- 2 - A 03 DFFE 0 2 0 1 |REG32B:2|:70
- 2 - A 24 DFFE 0 2 0 1 |REG32B:2|:72
- 4 - A 20 DFFE 0 2 0 1 |REG32B:2|:74
- 2 - A 23 DFFE 0 2 0 1 |REG32B:2|:76
- 5 - A 19 DFFE 0 2 0 1 |REG32B:2|:78
- 4 - A 24 DFFE 0 2 0 1 |REG32B:2|:80
- 6 - A 20 DFFE 0 2 0 1 |REG32B:2|:82
- 1 - A 14 DFFE 0 2 0 1 |REG32B:2|:84
- 4 - A 19 DFFE 0 2 0 1 |REG32B:2|:86
- 6 - A 24 DFFE 0 2 0 1 |REG32B:2|:88
- 8 - A 20 DFFE 0 2 0 1 |REG32B:2|:90
- 8 - A 13 DFFE 0 2 0 1 |REG32B:2|:92
- 2 - A 19 DFFE 0 2 0 1 |REG32B:2|:94
- 8 - A 24 DFFE 0 2 0 1 |REG32B:2|:96
- 4 - A 09 OR2 ! 3 0 0 4 |SELTIME:89|:725
- 4 - A 07 OR2 0 3 0 1 |SELTIME:89|:728
- 2 - A 09 AND2 3 0 0 4 |SELTIME:89|:735
- 5 - A 07 OR2 0 3 0 1 |SELTIME:89|:738
- 1 - A 09 OR2 ! 3 0 0 5 |SELTIME:89|:745
- 2 - A 07 OR2 0 3 0 1 |SELTIME:89|:748
- 8 - A 09 OR2 ! 3 0 0 4 |SELTIME:89|:755
- 3 - A 20 OR2 0 3 0 1 |SELTIME:89|:758
- 6 - A 09 OR2 ! 3 0 0 4 |SELTIME:89|:765
- 5 - A 20 OR2 0 3 0 1 |SELTIME:89|:768
- 7 - A 09 OR2 ! 3 0 0 5 |SELTIME:89|:775
- 7 - A 20 OR2 0 3 0 1 |SELTIME:89|:778
- 3 - A 09 OR2 ! 3 0 0 4 |SELTIME:89|:785
- 1 - A 20 OR2 0 3 0 5 |SELTIME:89|:788
- 8 - A 07 OR2 ! 0 3 0 1 |SELTIME:89|:794
- 3 - A 05 OR2 ! 0 2 0 1 |SELTIME:89|:801
- 1 - A 07 OR2 ! 0 4 0 1 |SELTIME:89|:802
- 1 - A 05 OR2 ! 0 4 0 1 |SELTIME:89|:803
- 6 - A 13 OR2 ! 0 2 0 1 |SELTIME:89|:810
- 7 - A 13 OR2 ! 0 4 0 1 |SELTIME:89|:811
- 2 - A 13 OR2 ! 0 4 0 4 |SELTIME:89|:812
- 4 - A 04 OR2 ! 0 3 0 1 |SELTIME:89|:818
- 5 - A 03 OR2 ! 0 3 0 1 |SELTIME:89|:821
- 6 - A 03 OR2 ! 0 3 0 1 |SELTIME:89|:824
- 1 - A 03 OR2 ! 0 3 0 1 |SELTIME:89|:827
- 6 - A 19 OR2 ! 0 3 0 1 |SELTIME:89|:830
- 7 - A 19 OR2 ! 0 3 0 1 |SELTIME:89|:833
- 1 - A 19 OR2 ! 0 3 0 4 |SELTIME:89|:836
- 5 - A 04 OR2 0 3 0 1 |SELTIME:89|:842
- 6 - A 04 OR2 0 3 0 1 |SELTIME:89|:845
- 8 - A 04 OR2 0 3 0 1 |SELTIME:89|:848
- 3 - A 24 OR2 0 3 0 1 |SELTIME:89|:851
- 5 - A 24 OR2 0 3 0 1 |SELTIME:89|:854
- 7 - A 24 OR2 0 3 0 1 |SELTIME:89|:857
- 1 - A 24 OR2 0 3 0 1 |SELTIME:89|:860
- 2 - A 16 DFFE 1 0 0 62 |TESTCTL:13|div2clk (|TESTCTL:13|:5)
- 1 - A 16 OR2 ! 1 1 0 32 |TESTCTL:13|:36
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: d:\edaplay\digital\test20\frequency\fry.rpt
fry
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 24/ 96( 25%) 20/ 48( 41%) 22/ 48( 45%) 0/16( 0%) 5/16( 31%) 0/16( 0%)
B: 3/ 96( 3%) 0/ 48( 0%) 2/ 48( 4%) 2/16( 12%) 2/16( 12%) 0/16( 0%)
C: 9/ 96( 9%) 0/ 48( 0%) 0/ 48( 0%) 8/16( 50%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 2/24( 8%) 0/4( 0%) 2/4( 50%) 0/4( 0%)
02: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
03: 2/24( 8%) 0/4( 0%) 2/4( 50%) 0/4( 0%)
04: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
05: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 2/24( 8%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 2/4( 50%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: d:\edaplay\digital\test20\frequency\fry.rpt
fry
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