reg32b.rpt

几个VHDL实现的源程序及其代码

89   -> - - - - - - - - - | - - - - - - - - | <-- load


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:               c:\maxplus2\1502d\test11\reg32b.rpt
reg32b

** LOGIC CELL INTERCONNECTIONS **

Logic Array Block 'G':

                           Logic cells placed in LAB 'G'
        +----------------- LC109 dout10
        | +--------------- LC110 dout11
        | | +------------- LC105 dout12
        | | | +----------- LC107 dout13
        | | | | +--------- LC104 dout14
        | | | | | +------- LC102 dout15
        | | | | | | +----- LC101 dout16
        | | | | | | | +--- LC99 dout17
        | | | | | | | | +- LC97 dout18
        | | | | | | | | | 
        | | | | | | | | |   Other LABs fed by signals
        | | | | | | | | |   that feed LAB 'G'
LC      | | | | | | | | | | A B C D E F G H |     Logic cells that feed LAB 'G':

Pin
14   -> * - - - - - - - - | - - - - - - * - | <-- din10
34   -> - * - - - - - - - | - - - - - - * - | <-- din11
37   -> - - * - - - - - - | - - - - - - * - | <-- din12
18   -> - - - * - - - - - | - - - - - - * - | <-- din13
19   -> - - - - * - - - - | - - - - - - * - | <-- din14
21   -> - - - - - * - - - | - - - - - - * - | <-- din15
23   -> - - - - - - * - - | - - - - - - * - | <-- din16
25   -> - - - - - - - * - | - - - - - - * - | <-- din17
9    -> - - - - - - - - * | - - - - - - * - | <-- din18
89   -> - - - - - - - - - | - - - - - - - - | <-- load


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:               c:\maxplus2\1502d\test11\reg32b.rpt
reg32b

** LOGIC CELL INTERCONNECTIONS **

Logic Array Block 'H':

                             Logic cells placed in LAB 'H'
        +------------------- LC126 dout0
        | +----------------- LC125 dout1
        | | +--------------- LC121 dout2
        | | | +------------- LC117 dout3
        | | | | +----------- LC120 dout4
        | | | | | +--------- LC115 dout5
        | | | | | | +------- LC123 dout6
        | | | | | | | +----- LC128 dout7
        | | | | | | | | +--- LC118 dout8
        | | | | | | | | | +- LC113 dout9
        | | | | | | | | | | 
        | | | | | | | | | |   Other LABs fed by signals
        | | | | | | | | | |   that feed LAB 'H'
LC      | | | | | | | | | | | A B C D E F G H |     Logic cells that feed LAB 'H':

Pin
11   -> * - - - - - - - - - | - - - - - - - * | <-- din0
24   -> - * - - - - - - - - | - - - - - - - * | <-- din1
26   -> - - * - - - - - - - | - - - - - - - * | <-- din2
27   -> - - - * - - - - - - | - - - - - - - * | <-- din3
7    -> - - - - * - - - - - | - - - - - - - * | <-- din4
8    -> - - - - - * - - - - | - - - - - - - * | <-- din5
22   -> - - - - - - * - - - | - - - - - - - * | <-- din6
39   -> - - - - - - - * - - | - - - - - - - * | <-- din7
29   -> - - - - - - - - * - | - - - - - - - * | <-- din8
16   -> - - - - - - - - - * | - - - - - - - * | <-- din9
89   -> - - - - - - - - - - | - - - - - - - - | <-- load


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:               c:\maxplus2\1502d\test11\reg32b.rpt
reg32b

** EQUATIONS **

din0     : INPUT;
din1     : INPUT;
din2     : INPUT;
din3     : INPUT;
din4     : INPUT;
din5     : INPUT;
din6     : INPUT;
din7     : INPUT;
din8     : INPUT;
din9     : INPUT;
din10    : INPUT;
din11    : INPUT;
din12    : INPUT;
din13    : INPUT;
din14    : INPUT;
din15    : INPUT;
din16    : INPUT;
din17    : INPUT;
din18    : INPUT;
din19    : INPUT;
din20    : INPUT;
din21    : INPUT;
din22    : INPUT;
din23    : INPUT;
din24    : INPUT;
din25    : INPUT;
din26    : INPUT;
din27    : INPUT;
din28    : INPUT;
din29    : INPUT;
din30    : INPUT;
din31    : INPUT;
load     : INPUT;

-- Node name is 'dout0' = ':96' 
-- Equation name is 'dout0', type is output 
 dout0   = DFFE( din0 $  GND, GLOBAL( load),  VCC,  VCC,  VCC);

-- Node name is 'dout1' = ':94' 
-- Equation name is 'dout1', type is output 
 dout1   = DFFE( din1 $  GND, GLOBAL( load),  VCC,  VCC,  VCC);

-- Node name is 'dout2' = ':92' 
-- Equation name is 'dout2', type is output 
 dout2   = DFFE( din2 $  GND, GLOBAL( load),  VCC,  VCC,  VCC);

-- Node name is 'dout3' = ':90' 
-- Equation name is 'dout3', type is output 
 dout3   = DFFE( din3 $  GND, GLOBAL( load),  VCC,  VCC,  VCC);

-- Node name is 'dout4' = ':88' 
-- Equation name is 'dout4', type is output 
 dout4   = DFFE( din4 $  GND, GLOBAL( load),  VCC,  VCC,  VCC);

-- Node name is 'dout5' = ':86' 
-- Equation name is 'dout5', type is output 
 dout5   = DFFE( din5 $  GND, GLOBAL( load),  VCC,  VCC,  VCC);

-- Node name is 'dout6' = ':84' 
-- Equation name is 'dout6', type is output 
 dout6   = DFFE( din6 $  GND, GLOBAL( load),  VCC,  VCC,  VCC);

-- Node name is 'dout7' = ':82' 
-- Equation name is 'dout7', type is output 
 dout7   = DFFE( din7 $  GND, GLOBAL( load),  VCC,  VCC,  VCC);

-- Node name is 'dout8' = ':80' 
-- Equation name is 'dout8', type is output 
 dout8   = DFFE( din8 $  GND, GLOBAL( load),  VCC,  VCC,  VCC);

-- Node name is 'dout9' = ':78' 
-- Equation name is 'dout9', type is output 
 dout9   = DFFE( din9 $  GND, GLOBAL( load),  VCC,  VCC,  VCC);

-- Node name is 'dout10' = ':76' 
-- Equation name is 'dout10', type is output 
 dout10  = DFFE( din10 $  GND, GLOBAL( load),  VCC,  VCC,  VCC);

-- Node name is 'dout11' = ':74' 
-- Equation name is 'dout11', type is output 
 dout11  = DFFE( din11 $  GND, GLOBAL( load),  VCC,  VCC,  VCC);

-- Node name is 'dout12' = ':72' 
-- Equation name is 'dout12', type is output 
 dout12  = DFFE( din12 $  GND, GLOBAL( load),  VCC,  VCC,  VCC);

-- Node name is 'dout13' = ':70' 
-- Equation name is 'dout13', type is output 
 dout13  = DFFE( din13 $  GND, GLOBAL( load),  VCC,  VCC,  VCC);

-- Node name is 'dout14' = ':68' 
-- Equation name is 'dout14', type is output 
 dout14  = DFFE( din14 $  GND, GLOBAL( load),  VCC,  VCC,  VCC);

-- Node name is 'dout15' = ':66' 
-- Equation name is 'dout15', type is output 
 dout15  = DFFE( din15 $  GND, GLOBAL( load),  VCC,  VCC,  VCC);

-- Node name is 'dout16' = ':64' 
-- Equation name is 'dout16', type is output 
 dout16  = DFFE( din16 $  GND, GLOBAL( load),  VCC,  VCC,  VCC);

-- Node name is 'dout17' = ':62' 
-- Equation name is 'dout17', type is output 
 dout17  = DFFE( din17 $  GND, GLOBAL( load),  VCC,  VCC,  VCC);

-- Node name is 'dout18' = ':60' 
-- Equation name is 'dout18', type is output 
 dout18  = DFFE( din18 $  GND, GLOBAL( load),  VCC,  VCC,  VCC);

-- Node name is 'dout19' = ':58' 
-- Equation name is 'dout19', type is output 
 dout19  = DFFE( din19 $  GND, GLOBAL( load),  VCC,  VCC,  VCC);

-- Node name is 'dout20' = ':56' 
-- Equation name is 'dout20', type is output 
 dout20  = DFFE( din20 $  GND, GLOBAL( load),  VCC,  VCC,  VCC);

-- Node name is 'dout21' = ':54' 
-- Equation name is 'dout21', type is output 
 dout21  = DFFE( din21 $  GND, GLOBAL( load),  VCC,  VCC,  VCC);

-- Node name is 'dout22' = ':52' 
-- Equation name is 'dout22', type is output 
 dout22  = DFFE( din22 $  GND, GLOBAL( load),  VCC,  VCC,  VCC);

-- Node name is 'dout23' = ':50' 
-- Equation name is 'dout23', type is output 
 dout23  = DFFE( din23 $  GND, GLOBAL( load),  VCC,  VCC,  VCC);

-- Node name is 'dout24' = ':48' 
-- Equation name is 'dout24', type is output 
 dout24  = DFFE( din24 $  GND, GLOBAL( load),  VCC,  VCC,  VCC);

-- Node name is 'dout25' = ':46' 
-- Equation name is 'dout25', type is output 
 dout25  = DFFE( din25 $  GND, GLOBAL( load),  VCC,  VCC,  VCC);

-- Node name is 'dout26' = ':44' 
-- Equation name is 'dout26', type is output 
 dout26  = DFFE( din26 $  GND, GLOBAL( load),  VCC,  VCC,  VCC);

-- Node name is 'dout27' = ':42' 
-- Equation name is 'dout27', type is output 
 dout27  = DFFE( din27 $  GND, GLOBAL( load),  VCC,  VCC,  VCC);

-- Node name is 'dout28' = ':40' 
-- Equation name is 'dout28', type is output 
 dout28  = DFFE( din28 $  GND, GLOBAL( load),  VCC,  VCC,  VCC);

-- Node name is 'dout29' = ':38' 
-- Equation name is 'dout29', type is output 
 dout29  = DFFE( din29 $  GND, GLOBAL( load),  VCC,  VCC,  VCC);

-- Node name is 'dout30' = ':36' 
-- Equation name is 'dout30', type is output 
 dout30  = DFFE( din30 $  GND, GLOBAL( load),  VCC,  VCC,  VCC);

-- Node name is 'dout31' = ':34' 
-- Equation name is 'dout31', type is output 
 dout31  = DFFE( din31 $  GND, GLOBAL( load),  VCC,  VCC,  VCC);



--     Shareable expanders that are duplicated in multiple LABs:
--     (none)




Project Information                        c:\maxplus2\1502d\test11\reg32b.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Standard

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'MAX7000S' family

      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      PARALLEL_EXPANDERS                  = off
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SOFT_BUFFER_INSERTION               = on
      SUBFACTOR_EXTRACTION                = on
      TURBO_BIT                           = on
      XOR_SYNTHESIS                       = on
      IGNORE_SOFT_BUFFERS                 = off
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      One-Hot State Machine Encoding      = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:00
   Fitter                                 00:00:00
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:03
   --------------------------             --------
   Total Time                             00:00:03


Memory Allocated
-----------------

Peak memory allocated during compilation  = 4,135K