📄 seltime.rpt
字号:
| that feed LAB 'F'
LC | | A B C D E F G H | Logic cells that feed LAB 'F':
Pin
34 -> * | - - - - - * - - | <-- din0
54 -> * | - - - - - * - - | <-- din4
25 -> * | - - - - - * - - | <-- din8
35 -> * | - - - - - * - - | <-- din12
6 -> * | - - - - - * - - | <-- din16
20 -> * | - - - - - * - - | <-- din20
15 -> * | - - - - - * - - | <-- din24
12 -> * | - - - - - * - * | <-- din25
11 -> * | - - - - - * - * | <-- sel0
10 -> * | - - - - - * - * | <-- sel1
9 -> * | - - - - - * - * | <-- sel2
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: c:\windows\desktop\fr\frequency\seltime.rpt
seltime
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'H':
Logic cells placed in LAB 'H'
+------- LC115 daout1
| +----- LC117 daout2
| | +--- LC118 daout3
| | | +- LC113 ~788~1
| | | |
| | | | Other LABs fed by signals
| | | | that feed LAB 'H'
LC | | | | | A B C D E F G H | Logic cells that feed LAB 'H':
LC113-> - - * - | - - - - - - - * | <-- ~788~1
Pin
33 -> * - - - | - - - - - - - * | <-- din1
48 -> - * - - | - - - - - - - * | <-- din2
52 -> - - - * | - - - - - - - * | <-- din3
22 -> * - - - | - - - - - - - * | <-- din5
30 -> - * - - | - - - - - - - * | <-- din6
28 -> - - - * | - - - - - - - * | <-- din7
24 -> * - - - | - - - - - - - * | <-- din9
39 -> - * - - | - - - - - - - * | <-- din10
36 -> - - - * | - - - - - - - * | <-- din11
37 -> * - - - | - - - - - - - * | <-- din13
41 -> - * - - | - - - - - - - * | <-- din14
8 -> - - * - | - - - - - - - * | <-- din15
5 -> * - - - | - - - - - - - * | <-- din17
4 -> - * - - | - - - - - - - * | <-- din18
21 -> - - - * | - - - - - - - * | <-- din19
18 -> * - - - | - - - - - - - * | <-- din21
17 -> - * - - | - - - - - - - * | <-- din22
16 -> - - * - | - - - - - - - * | <-- din23
12 -> * - - - | - - - - - * - * | <-- din25
31 -> * * - - | - - - - - - - * | <-- din26
29 -> - * * - | - - - - - - - * | <-- din27
27 -> - - * - | - - - - - - - * | <-- din28
11 -> * * * * | - - - - - * - * | <-- sel0
10 -> * * * * | - - - - - * - * | <-- sel1
9 -> * * * * | - - - - - * - * | <-- sel2
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: c:\windows\desktop\fr\frequency\seltime.rpt
seltime
** EQUATIONS **
din0 : INPUT;
din1 : INPUT;
din2 : INPUT;
din3 : INPUT;
din4 : INPUT;
din5 : INPUT;
din6 : INPUT;
din7 : INPUT;
din8 : INPUT;
din9 : INPUT;
din10 : INPUT;
din11 : INPUT;
din12 : INPUT;
din13 : INPUT;
din14 : INPUT;
din15 : INPUT;
din16 : INPUT;
din17 : INPUT;
din18 : INPUT;
din19 : INPUT;
din20 : INPUT;
din21 : INPUT;
din22 : INPUT;
din23 : INPUT;
din24 : INPUT;
din25 : INPUT;
din26 : INPUT;
din27 : INPUT;
din28 : INPUT;
sel0 : INPUT;
sel1 : INPUT;
sel2 : INPUT;
-- Node name is 'daout0' = ':860'
-- Equation name is 'daout0', type is output
daout0 = LCELL( _EQ001 $ _EQ002);
_EQ001 = !din20 & !sel0 & sel1 & !sel2 & _X001 & _X002 & _X003 & _X004
# !din12 & !sel0 & !sel1 & sel2 & _X001 & _X002 & _X003 & _X004
# !din24 & sel0 & !sel1 & !sel2 & _X001 & _X002 & _X003 & _X004
# !din25 & !sel0 & !sel1 & !sel2 & _X001 & _X002 & _X003 & _X004;
_X001 = EXP(!din0 & sel0 & sel1 & sel2);
_X002 = EXP(!din4 & !sel0 & sel1 & sel2);
_X003 = EXP(!din16 & sel0 & sel1 & !sel2);
_X004 = EXP(!din8 & sel0 & !sel1 & sel2);
_EQ002 = _X001 & _X002 & _X003 & _X004;
_X001 = EXP(!din0 & sel0 & sel1 & sel2);
_X002 = EXP(!din4 & !sel0 & sel1 & sel2);
_X003 = EXP(!din16 & sel0 & sel1 & !sel2);
_X004 = EXP(!din8 & sel0 & !sel1 & sel2);
-- Node name is 'daout1' = ':836'
-- Equation name is 'daout1', type is output
daout1 = LCELL( _EQ003 $ _EQ004);
_EQ003 = !din21 & !sel0 & sel1 & !sel2 & _X005 & _X006 & _X007 & _X008
# !din13 & !sel0 & !sel1 & sel2 & _X005 & _X006 & _X007 & _X008
# !din25 & sel0 & !sel1 & !sel2 & _X005 & _X006 & _X007 & _X008
# !din26 & !sel0 & !sel1 & !sel2 & _X005 & _X006 & _X007 & _X008;
_X005 = EXP(!din1 & sel0 & sel1 & sel2);
_X006 = EXP(!din5 & !sel0 & sel1 & sel2);
_X007 = EXP(!din17 & sel0 & sel1 & !sel2);
_X008 = EXP(!din9 & sel0 & !sel1 & sel2);
_EQ004 = _X005 & _X006 & _X007 & _X008;
_X005 = EXP(!din1 & sel0 & sel1 & sel2);
_X006 = EXP(!din5 & !sel0 & sel1 & sel2);
_X007 = EXP(!din17 & sel0 & sel1 & !sel2);
_X008 = EXP(!din9 & sel0 & !sel1 & sel2);
-- Node name is 'daout2' = ':812'
-- Equation name is 'daout2', type is output
daout2 = LCELL( _EQ005 $ _EQ006);
_EQ005 = !din22 & !sel0 & sel1 & !sel2 & _X009 & _X010 & _X011 & _X012
# !din14 & !sel0 & !sel1 & sel2 & _X009 & _X010 & _X011 & _X012
# !din26 & sel0 & !sel1 & !sel2 & _X009 & _X010 & _X011 & _X012
# !din27 & !sel0 & !sel1 & !sel2 & _X009 & _X010 & _X011 & _X012;
_X009 = EXP(!din2 & sel0 & sel1 & sel2);
_X010 = EXP(!din6 & !sel0 & sel1 & sel2);
_X011 = EXP(!din18 & sel0 & sel1 & !sel2);
_X012 = EXP(!din10 & sel0 & !sel1 & sel2);
_EQ006 = _X009 & _X010 & _X011 & _X012;
_X009 = EXP(!din2 & sel0 & sel1 & sel2);
_X010 = EXP(!din6 & !sel0 & sel1 & sel2);
_X011 = EXP(!din18 & sel0 & sel1 & !sel2);
_X012 = EXP(!din10 & sel0 & !sel1 & sel2);
-- Node name is 'daout3' = ':788'
-- Equation name is 'daout3', type is output
daout3 = LCELL( _EQ007 $ !_LC113);
_EQ007 = !din23 & !_LC113 & !sel0 & sel1 & !sel2
# !din15 & !_LC113 & !sel0 & !sel1 & sel2
# !din27 & !_LC113 & sel0 & !sel1 & !sel2
# !din28 & !_LC113 & !sel0 & !sel1 & !sel2;
-- Node name is '~788~1'
-- Equation name is '~788~1', location is LC113, type is buried.
-- synthesized logic cell
_LC113 = LCELL( _EQ008 $ GND);
_EQ008 = !din3 & sel0 & sel1 & sel2
# !din7 & !sel0 & sel1 & sel2
# !din19 & sel0 & sel1 & !sel2
# !din11 & sel0 & !sel1 & sel2;
-- Shareable expanders that are duplicated in multiple LABs:
-- (none)
Project Information c:\windows\desktop\fr\frequency\seltime.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'MAX7000S' family
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
PARALLEL_EXPANDERS = off
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SOFT_BUFFER_INSERTION = on
SUBFACTOR_EXTRACTION = on
TURBO_BIT = on
XOR_SYNTHESIS = on
IGNORE_SOFT_BUFFERS = off
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = off
Automatic Global Clear = off
Automatic Global Preset = off
Automatic Global Output Enable = off
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
One-Hot State Machine Encoding = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = on
Verilog Netlist Writer = off
VHDL Netlist Writer = off
ADT PALACE Compilation = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:01
Database Builder 00:00:00
Logic Synthesizer 00:00:01
Partitioner 00:00:00
Fitter 00:00:01
Timing SNF Extractor 00:00:00
EDIF Netlist Writer 00:00:00
Assembler 00:00:02
-------------------------- --------
Total Time 00:00:05
Memory Allocated
-----------------
Peak memory allocated during compilation = 5,898K
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