📄 seltime.rpt
字号:
Project Information c:\windows\desktop\fr\frequency\seltime.rpt
MAX+plus II Compiler Report File
Version 10.2 07/10/2002
Compiled: 10/10/2002 10:44:39
Copyright (C) 1988-2002 Altera Corporation
Any megafunction design, and related net list (encrypted or decrypted),
support information, device programming or simulation file, and any other
associated documentation or information provided by Altera or a partner
under Altera's Megafunction Partnership Program may be used only to
program PLD devices (but not masked PLD devices) from Altera. Any other
use of such megafunction design, net list, support information, device
programming or simulation file, or any other related documentation or
information is prohibited for any other purpose, including, but not
limited to modification, reverse engineering, de-compiling, or use with
any other silicon devices, unless such use is explicitly licensed under
a separate agreement with Altera or a megafunction partner. Title to
the intellectual property, including patents, copyrights, trademarks,
trade secrets, or maskworks, embodied in any such megafunction design,
net list, support information, device programming or simulation file, or
any other related documentation or information provided by Altera or a
megafunction partner, remains with Altera, the megafunction partner, or
their respective licensors. No other licenses, including any licenses
needed under any third party's intellectual property, are provided herein.
***** Project compilation was successful
SELTIME
** DEVICE SUMMARY **
Chip/ Input Output Bidir Shareable
POF Device Pins Pins Pins LCs Expanders % Utilized
seltime EPM7128SLC84-15 32 4 0 5 12 3 %
User Pins: 32 4 0
Project Information c:\windows\desktop\fr\frequency\seltime.rpt
** PROJECT COMPILATION MESSAGES **
Warning: Ignored unnecessary INPUT pin 'din31'
Warning: Ignored unnecessary INPUT pin 'din30'
Warning: Ignored unnecessary INPUT pin 'din29'
Device-Specific Information: c:\windows\desktop\fr\frequency\seltime.rpt
seltime
***** Logic for device 'seltime' compiled without errors.
Device: EPM7128SLC84-15
Device Options:
Turbo Bit = ON
Security Bit = OFF
Enable JTAG Support = ON
User Code = ffff
MultiVolt I/O = OFF
R R R R R
E E E E E
V S S S S S d
d d d d C E E E V E E a
s s s i i i i C R R R C R R o
e e e n G n n n I G G G G G V V V C V V u
l l l 1 N 1 1 1 N N N N N N E E E I E E t
0 1 2 5 D 6 7 8 T D D D D D D D D O D D 3
-----------------------------------------------------------------_
/ 11 10 9 8 7 6 5 4 3 2 1 84 83 82 81 80 79 78 77 76 75 |
din25 | 12 74 | daout2
VCCIO | 13 73 | daout1
#TDI | 14 72 | GND
din24 | 15 71 | #TDO
din23 | 16 70 | RESERVED
din22 | 17 69 | RESERVED
din21 | 18 68 | RESERVED
GND | 19 67 | RESERVED
din20 | 20 66 | VCCIO
din19 | 21 65 | RESERVED
din5 | 22 EPM7128SLC84-15 64 | RESERVED
#TMS | 23 63 | RESERVED
din9 | 24 62 | #TCK
din8 | 25 61 | RESERVED
VCCIO | 26 60 | RESERVED
din28 | 27 59 | GND
din7 | 28 58 | RESERVED
din27 | 29 57 | RESERVED
din6 | 30 56 | RESERVED
din26 | 31 55 | daout0
GND | 32 54 | din4
|_ 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 _|
------------------------------------------------------------------
d d d d d V d R d G V R R R G d R R R d V
i i i i i C i E i N C E E E N i E E E i C
n n n n n C n S n D C S S S D n S S S n C
1 0 1 1 1 I 1 E 1 I E E E 2 E E E 3 I
2 1 3 O 0 R 4 N R R R R R R O
V T V V V V V V
E E E E E E E
D D D D D D D
N.C. = No Connect. This pin has no internal connection to the device.
VCCINT = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
VCCIO = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
GND = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.
^ = Dedicated configuration pin.
+ = Reserved configuration pin, which is tri-stated during user mode.
* = Reserved configuration pin, which drives out in user mode.
PDn = Power Down pin.
@ = Special-purpose pin.
# = JTAG Boundary-Scan Testing/In-System Programming or Configuration Pin. The JTAG inputs TMS and TDI should be tied to VCC and TCK should be tied to GND when not in use.
& = JTAG pin used for I/O. When used as user I/O, JTAG pins must be kept stable before and during configuration. JTAG pin stability prevents accidental loading of JTAG instructions.
Device-Specific Information: c:\windows\desktop\fr\frequency\seltime.rpt
seltime
** RESOURCE USAGE **
Shareable External
Logic Array Block Logic Cells I/O Pins Expanders Interconnect
A: LC1 - LC16 0/16( 0%) 8/ 8(100%) 0/16( 0%) 0/36( 0%)
B: LC17 - LC32 0/16( 0%) 8/ 8(100%) 0/16( 0%) 0/36( 0%)
C: LC33 - LC48 0/16( 0%) 8/ 8(100%) 0/16( 0%) 0/36( 0%)
D: LC49 - LC64 0/16( 0%) 7/ 8( 87%) 0/16( 0%) 0/36( 0%)
E: LC65 - LC80 0/16( 0%) 2/ 8( 25%) 0/16( 0%) 0/36( 0%)
F: LC81 - LC96 1/16( 6%) 3/ 8( 37%) 5/16( 31%) 11/36( 30%)
G: LC97 - LC112 0/16( 0%) 1/ 8( 12%) 0/16( 0%) 0/36( 0%)
H: LC113 - LC128 4/16( 25%) 3/ 8( 37%) 11/16( 68%) 26/36( 72%)
Total dedicated input pins used: 0/4 ( 0%)
Total I/O pins used: 40/64 ( 62%)
Total logic cells used: 5/128 ( 3%)
Total shareable expanders used: 12/128 ( 9%)
Total Turbo logic cells used: 5/128 ( 3%)
Total shareable expanders not available (n/a): 4/128 ( 3%)
Average fan-in: 9.60
Total fan-in: 48
Total input pins required: 32
Total fast input logic cells required: 0
Total output pins required: 4
Total bidirectional pins required: 0
Total reserved pins required 4
Total logic cells required: 5
Total flipflops required: 0
Total product terms required: 36
Total logic cells lending parallel expanders: 0
Total shareable expanders in database: 12
Synthesized logic cells: 1/ 128 ( 0%)
Device-Specific Information: c:\windows\desktop\fr\frequency\seltime.rpt
seltime
** INPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
34 (61) (D) INPUT 0 0 0 0 0 1 0 din0
33 (64) (D) INPUT 0 0 0 0 0 1 0 din1
48 (72) (E) INPUT 0 0 0 0 0 1 0 din2
52 (80) (E) INPUT 0 0 0 0 0 0 1 din3
54 (83) (F) INPUT 0 0 0 0 0 1 0 din4
22 (17) (B) INPUT 0 0 0 0 0 1 0 din5
30 (37) (C) INPUT 0 0 0 0 0 1 0 din6
28 (40) (C) INPUT 0 0 0 0 0 0 1 din7
25 (45) (C) INPUT 0 0 0 0 0 1 0 din8
24 (46) (C) INPUT 0 0 0 0 0 1 0 din9
39 (53) (D) INPUT 0 0 0 0 0 1 0 din10
36 (57) (D) INPUT 0 0 0 0 0 0 1 din11
35 (59) (D) INPUT 0 0 0 0 0 1 0 din12
37 (56) (D) INPUT 0 0 0 0 0 1 0 din13
41 (49) (D) INPUT 0 0 0 0 0 1 0 din14
8 (11) (A) INPUT 0 0 0 0 0 1 0 din15
6 (13) (A) INPUT 0 0 0 0 0 1 0 din16
5 (14) (A) INPUT 0 0 0 0 0 1 0 din17
4 (16) (A) INPUT 0 0 0 0 0 1 0 din18
21 (19) (B) INPUT 0 0 0 0 0 0 1 din19
20 (21) (B) INPUT 0 0 0 0 0 1 0 din20
18 (24) (B) INPUT 0 0 0 0 0 1 0 din21
17 (25) (B) INPUT 0 0 0 0 0 1 0 din22
16 (27) (B) INPUT 0 0 0 0 0 1 0 din23
15 (29) (B) INPUT 0 0 0 0 0 1 0 din24
12 (3) (A) INPUT 0 0 0 0 0 2 0 din25
31 (35) (C) INPUT 0 0 0 0 0 2 0 din26
29 (38) (C) INPUT 0 0 0 0 0 2 0 din27
27 (43) (C) INPUT 0 0 0 0 0 1 0 din28
11 (5) (A) INPUT 0 0 0 0 0 4 1 sel0
10 (6) (A) INPUT 0 0 0 0 0 4 1 sel1
9 (8) (A) INPUT 0 0 0 0 0 4 1 sel2
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: c:\windows\desktop\fr\frequency\seltime.rpt
seltime
** OUTPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
55 85 F OUTPUT t 5 0 1 11 0 0 0 daout0
73 115 H OUTPUT t 5 0 1 11 0 0 0 daout1
74 117 H OUTPUT t 5 0 1 11 0 0 0 daout2
75 118 H OUTPUT t 1 0 1 7 1 0 0 daout3
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: c:\windows\desktop\fr\frequency\seltime.rpt
seltime
** BURIED LOGIC **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
- 113 H SOFT s t 0 0 0 7 0 1 0 ~788~1
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: c:\windows\desktop\fr\frequency\seltime.rpt
seltime
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'F':
Logic cells placed in LAB 'F'
+- LC85 daout0
|
| Other LABs fed by signals
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -