seltime.vhd

几个VHDL实现的源程序及其代码

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity seltime is
port(
     din : in std_logic_vector(31 downto 0);
     daout: out std_logic_vector(3 downto 0);
     sel : in std_logic_vector(2 downto 0));
end seltime;

architecture behav of seltime is
begin
process(sel,din(31 downto 0))
begin
case sel is
when "111"=>daout<=din(3 downto 0);
when "110"=>daout<=din(7 downto 4);
when "101"=>daout<=din(11 downto 8);
when "100"=>daout<=din(15 downto 12);
when "011"=>daout<=din(19 downto 16);
when "010"=>daout<=din(23 downto 20);
when "001"=>daout<=din(27 downto 24);
when "000"=>daout<=din(31 downto 25);
when others=>daout<="XXXX";
end case;
end process;
end behav;