cnt10.rpt

几个VHDL实现的源程序及其代码

r = Fitter-inserted logic cell
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.


Device-Specific Information:                c:\maxplus2\1502d\test11\cnt10.rpt
cnt10

** OUTPUTS **

                                         Shareable
                                         Expanders     Fan-In    Fan-Out
 Pin     LC  LAB  Primitive    Code   Total Shared n/a INP  FBK  OUT  FBK  Name
  77    123    H     OUTPUT      t        0      0   0    0    4    0    0  carry_out
  76    120    H         FF   +  t        0      0   0    2    4    5    0  cq0 (:12)
  75    118    H         FF   +  t        0      0   0    2    3    5    0  cq1 (:11)
  74    117    H         FF   +  t        0      0   0    2    4    4    0  cq2 (:10)
  73    115    H         FF   +  t        1      0   0    2    4    5    0  cq3 (:9)


Code:

s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell


Device-Specific Information:                c:\maxplus2\1502d\test11\cnt10.rpt
cnt10

** LOGIC CELL INTERCONNECTIONS **

Logic Array Block 'H':

                   Logic cells placed in LAB 'H'
        +--------- LC123 carry_out
        | +------- LC120 cq0
        | | +----- LC118 cq1
        | | | +--- LC117 cq2
        | | | | +- LC115 cq3
        | | | | | 
        | | | | |   Other LABs fed by signals
        | | | | |   that feed LAB 'H'
LC      | | | | | | A B C D E F G H |     Logic cells that feed LAB 'H':
LC120-> * * * * * | - - - - - - - * | <-- cq0
LC118-> * * * * * | - - - - - - - * | <-- cq1
LC117-> * * - * * | - - - - - - - * | <-- cq2
LC115-> * * * * * | - - - - - - - * | <-- cq3

Pin
83   -> - - - - - | - - - - - - - - | <-- clk
12   -> - * * * * | - - - - - - - * | <-- clr
11   -> - * * * * | - - - - - - - * | <-- ena


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:                c:\maxplus2\1502d\test11\cnt10.rpt
cnt10

** EQUATIONS **

clk      : INPUT;
clr      : INPUT;
ena      : INPUT;

-- Node name is 'carry_out' 
-- Equation name is 'carry_out', location is LC123, type is output.
 carry_out = LCELL( _EQ001 $  GND);
  _EQ001 =  cq0 & !cq1 & !cq2 &  cq3;

-- Node name is 'cq0' = 'cqi0' 
-- Equation name is 'cq0', location is LC120, type is output.
 cq0     = DFFE( _EQ002 $  GND, GLOBAL( clk), !clr,  VCC,  VCC);
  _EQ002 = !cq0 & !cq1 & !cq2 &  cq3 &  ena
         # !cq0 & !cq3 &  ena
         #  cq0 & !ena;

-- Node name is 'cq1' = 'cqi1' 
-- Equation name is 'cq1', location is LC118, type is output.
 cq1     = DFFE( _EQ003 $  GND, GLOBAL( clk), !clr,  VCC,  VCC);
  _EQ003 = !cq0 &  cq1 & !cq3 &  ena
         #  cq0 & !cq1 & !cq3 &  ena
         #  cq1 & !ena;

-- Node name is 'cq2' = 'cqi2' 
-- Equation name is 'cq2', location is LC117, type is output.
 cq2     = TFFE( _EQ004, GLOBAL( clk), !clr,  VCC,  VCC);
  _EQ004 =  cq0 &  cq1 & !cq2 & !cq3 &  ena
         #  cq0 &  cq1 &  cq2 &  ena
         #  cq2 &  cq3 &  ena;

-- Node name is 'cq3' = 'cqi3' 
-- Equation name is 'cq3', location is LC115, type is output.
 cq3     = DFFE( _EQ005 $  GND, GLOBAL( clk), !clr,  VCC,  VCC);
  _EQ005 = !cq0 & !cq1 & !cq2 &  cq3 &  ena &  _X001
         #  cq0 &  cq1 &  cq2 & !cq3 &  ena
         #  cq3 & !ena;
  _X001  = EXP( cq0 &  cq1 &  cq2);



--     Shareable expanders that are duplicated in multiple LABs:
--     (none)




Project Information                         c:\maxplus2\1502d\test11\cnt10.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Standard

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'MAX7000S' family

      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      PARALLEL_EXPANDERS                  = off
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SOFT_BUFFER_INSERTION               = on
      SUBFACTOR_EXTRACTION                = on
      TURBO_BIT                           = on
      XOR_SYNTHESIS                       = on
      IGNORE_SOFT_BUFFERS                 = off
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      One-Hot State Machine Encoding      = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:02
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:00
   Fitter                                 00:00:00
   Timing SNF Extractor                   00:00:01
   Assembler                              00:00:04
   --------------------------             --------
   Total Time                             00:00:07


Memory Allocated
-----------------

Peak memory allocated during compilation  = 3,800K