74ls138_edcoder.vhd

来自「常用集成器件源码,主要为74系列源码,用vhdl编写」· VHDL 代码 · 共 30 行

library ieee;
use ieee.std_logic_1164.all;
entity decoder_74LS138 is
port(g1,g2a,g2b:in std_logic;
      a,b,c:in std_logic;
     y:out std_logic_vector(7 downto 0));
end decoder_74LS138;
architecture rtl_are of decoder_74LS138 is
signal comb :std_logic_vector(2 downto 0);
begin
comb<=c&b&a;
process(g1,g2a,g2b,comb)
begin
if(g1='1' and g2a='0' and g2b='0')then
case comb is
when "000"=>y<="11111110";
when "001"=>y<="11111101";
when "010"=>y<="11111011";
when "011"=>y<="11110111";
when "100"=>y<="11101111";
when "101"=>y<="11011111";
when "110"=>y<="10111111";
when "111"=>y<="01111111";
when others=>y<="XXXXXXXX";
end case;
else
y<="11111111";
end if;
end process;
end rtl_are;