tri_gate三态门.vhd

常用集成器件源码,主要为74系列源码,用vhdl编写

library ieee;
use ieee.std_logic_1164.all;
entity tri_gate is
port(din:in std_logic;
     en:in std_logic;
     dout:out std_logic);
end tri_gate;
architecture behave_are of tri_gate is
begin
process(din, en)
begin
if(en='1')then
dout<=din;
else
dout<='Z';
end if;
end process;
end behave_are;