与或非门.vhd

常用集成器件源码,主要为74系列源码,用vhdl编写

library ieee;
use ieee.std_logic_1164.all;
entity basic_gate is
port(a:in std_logic;
     b:in std_logic;
     c1:out std_logic;
     c2:out std_logic;
     c3:out std_logic;
     c4:out std_logic;
     c5:out std_logic);
end basic_gate;
architecture behave_are of basic_gate is
begin
p1:process(a,b)
begin
c1<=a or b;
end process p1;
p2:process(a)
begin
c2<=not a;
end process p2;
p3:process(a,b)
begin
c3<=a nand b;
end process p3;
p4:process(a,b)
begin
c4<=a nor b;
end process p4;
p5:process(a,b)
begin
c5<=a xor b;
end process p5;
end behave_are;