74ls148_encoder.vhd

常用集成器件源码,主要为74系列源码,用vhdl编写

library ieee;
use ieee.std_logic_1164.all;
entity pri_encoder is
port(d:in std_logic_vector(7 downto 0);
     e1:in std_logic;
     q:out std_logic_vector(2 downto 0);
     gs,e0:out std_logic);
end pri_encoder;
architecture rtl_are of pri_encoder is
begin
process(e1,d)
begin
if(e1='1')then
q<="111";
gs<='1';
e0<='1';
elsif(d="11111111" and e1='0')then
q<="111";
gs<='1';
e0<='0';
elsif(d(7)='0' and e1='0')then
q<="000";
gs<='0';
e0<='1';
elsif(d(6)='0' and e1='0')then
q<="001";
gs<='0';
e0<='1';
elsif(d(5)='0' and e1='0')then
q<="010";
gs<='0';
e0<='1';
elsif(d(4)='0' and e1='0')then
q<="011";
gs<='0';
e0<='1';
elsif(d(3)='0' and e1='0')then
q<="100";
gs<='0';
e0<='1';
elsif(d(2)='0' and e1='0')then
q<="101";
gs<='0';
e0<='1';
elsif(d(1)='0' and e1='0')then
q<="110";
gs<='0';
e0<='1';
elsif(d(1)='0' and e1='0')then
q<="111";
gs<='0';
e0<='1';
end if;
end process;
end rtl_are;