and3_gate.vhd

常用集成器件源码,主要为74系列源码,用vhdl编写

library ieee;
use ieee.std_logic_1164.all;
entity and3_gate is
port(a:in std_logic;
     b:in std_logic;
     c:in std_logic;
     y:out std_logic);
end and3_gate;
architecture behave_are of and3_gate is
begin
process(a,b,c)
begin
y<=a and b and c;
end process;
end behave_are;