缓冲器.vhd

常用集成器件源码,主要为74系列源码,用vhdl编写

library ieee;
use ieee.std_logic_1164.all;
entity bidir_bus_buff8 is
port(a,b:inout std_logic_vector(7 downto 0);
     en:in std_logic;
     dr:in std_logic);
end bidir_bus_buff8;
architecture rtl_are of bidir_bus_buff8 is
signal aout,bout:std_logic_vector(7 downto 0);
begin
process(a,b,dr,en)
begin
if(en='0' and dr='1')then
bout<=a;
elsif(en='0' and dr='1')then
aout<=b;
else
aout<="ZZZZZZZZ";
bout<="ZZZZZZZZ";
END IF;
b<=bout;
a<=aout;
end process;
end rtl_are;