2输入与门.vhd

常用集成器件源码,主要为74系列源码,用vhdl编写

library ieee;
use ieee.std_logic_1164.all;
entity and2_gate is
port(a:in std_logic;
     b:in std_logic;
     c:out std_logic);
end and2_gate;
architecture behave_are of and2_gate is
begin
process(a,b)
begin
c<=a and b;
end process;
end behave_are;