s3.ucf

VHDL FFT SOURCECODE great one

#========================================================
#    Pin assigbment for Xilinx 
#    Spartan-3 Starter board
#========================================================

#========================================================
# clock and reset
#========================================================
NET "clk"    LOC = "T9" ;
NET "reset"  LOC = "L14";

#========================================================
# buttons & switches 
#========================================================
# 4 push buttons 
NET "btn<0>"   LOC = "M13";
NET "btn<1>"   LOC = "M14";
NET "btn<2>"   LOC = "L13";
#NET "btn<3>"  LOC = "L14";  #btn<3> also used as reset

# 8 slide switches
NET "sw<0>"  LOC = "F12";
NET "sw<1>"  LOC = "G12";
NET "sw<2>"  LOC = "H14";
NET "sw<3>"  LOC = "H13";
NET "sw<4>"  LOC = "J14";
NET "sw<5>"  LOC = "J13";
NET "sw<6>"  LOC = "K14";
NET "sw<7>"  LOC = "K13";

#========================================================
# RS232
#========================================================
NET "rx"  LOC = "T13" | DRIVE=8 | SLEW=SLOW;
NET "tx"  LOC = "R13" | DRIVE=8 | SLEW=SLOW;

#========================================================
# 4-digit time-multiplexed 7-segment LED display
#========================================================
# digit enable
NET "an<0>"  LOC = "D14";
NET "an<1>"  LOC = "G14";
NET "an<2>"  LOC = "F14";
NET "an<3>"  LOC = "E13";

# 7-segment led segments 
NET "sseg<7>"  LOC = "P16"; # dicimal point
NET "sseg<6>"  LOC = "E14"; # segment a
NET "sseg<5>"  LOC = "G13"; # segment b
NET "sseg<4>"  LOC = "N15"; # segment c
NET "sseg<3>"  LOC = "P15"; # segment d
NET "sseg<2>"  LOC = "R16"; # segment e
NET "sseg<1>"  LOC = "F13"; # segment f 
NET "sseg<0>"  LOC = "N16"; # segment g 

#========================================================
# 8 discrete led
#========================================================
NET "led<0>"  LOC = "K12";
NET "led<1>"  LOC = "P14";
NET "led<2>"  LOC = "L12";
NET "led<3>"  LOC = "N14";
NET "led<4>"  LOC = "P13";
NET "led<5>"  LOC = "N12";
NET "led<6>"  LOC = "P12";
NET "led<7>"  LOC = "P11";

#========================================================
# VGA outputs
#========================================================
NET "rgb<2>"  LOC = "R12" | DRIVE=8 | SLEW=FAST;
NET "rgb<1>"  LOC = "T12" | DRIVE=8 | SLEW=FAST;
NET "rgb<0>"  LOC = "R11" | DRIVE=8 | SLEW=FAST;
NET "vsync"   LOC = "T10" | DRIVE=8 | SLEW=FAST;
NET "hsync"   LOC = "R9"  | DRIVE=8 | SLEW=FAST;

#========================================================
# PS2 port 
#========================================================
NET "ps2c" LOC="M16" | IOSTANDARD=LVCMOS33 | DRIVE=8 |SLEW=SLOW; 
NET "ps2d" LOC="M15" | IOSTANDARD=LVCMOS33 | DRIVE=8 |SLEW=SLOW;

#========================================================
# two SRAM chips
#========================================================
# shared 18-bit memory addres
NET "ad<17>"  LOC="L3" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
NET "ad<16>"  LOC="K5" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
NET "ad<15>"  LOC="K3" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
NET "ad<14>"  LOC="J3" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
NET "ad<13>"  LOC="J4" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
NET "ad<12>"  LOC="H4" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
NET "ad<11>"  LOC="H3" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
NET "ad<10>"  LOC="G5" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
NET "ad<9>"   LOC="E4" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
NET "ad<8>"   LOC="E3" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
NET "ad<7>"   LOC="F4" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
NET "ad<6>"   LOC="F3" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
NET "ad<5>"   LOC="G4" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
NET "ad<4>"   LOC="L4" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
NET "ad<3>"   LOC="M3" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
NET "ad<2>"   LOC="M4" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
NET "ad<1>"   LOC="N3" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
NET "ad<0>"   LOC="L5" | IOSTANDARD = LVCMOS33 | SLEW=FAST;

# shared oe, we
NET "oe_n"    LOC="K4" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
NET "we_n"    LOC="G3" | IOSTANDARD = LVCMOS33 | SLEW=FAST;

# sram chip 1 data, ce, ub, lb
NET "dio_a<15>" LOC="R1" | IOSTANDARD=LVCMOS33 | SLEW=FAST;
NET "dio_a<14>" LOC="P1" | IOSTANDARD=LVCMOS33 | SLEW=FAST;
NET "dio_a<13>" LOC="L2" | IOSTANDARD=LVCMOS33 | SLEW=FAST;
NET "dio_a<12>" LOC="J2" | IOSTANDARD=LVCMOS33 | SLEW=FAST;
NET "dio_a<11>" LOC="H1" | IOSTANDARD=LVCMOS33 | SLEW=FAST;
NET "dio_a<10>" LOC="F2" | IOSTANDARD=LVCMOS33 | SLEW=FAST;
NET "dio_a<9>"  LOC="P8" | IOSTANDARD=LVCMOS33 | SLEW=FAST;
NET "dio_a<8>"  LOC="D3" | IOSTANDARD=LVCMOS33 | SLEW=FAST;
NET "dio_a<7>"  LOC="B1" | IOSTANDARD=LVCMOS33 | SLEW=FAST;
NET "dio_a<6>"  LOC="C1" | IOSTANDARD=LVCMOS33 | SLEW=FAST;
NET "dio_a<5>"  LOC="C2" | IOSTANDARD=LVCMOS33 | SLEW=FAST;
NET "dio_a<4>"  LOC="R5" | IOSTANDARD=LVCMOS33 | SLEW=FAST;
NET "dio_a<3>"  LOC="T5" | IOSTANDARD=LVCMOS33 | SLEW=FAST;
NET "dio_a<2>"  LOC="R6" | IOSTANDARD=LVCMOS33 | SLEW=FAST;
NET "dio_a<1>"  LOC="T8" | IOSTANDARD=LVCMOS33 | SLEW=FAST;
NET "dio_a<0>"  LOC="N7" | IOSTANDARD=LVCMOS33 | SLEW=FAST;
NET "ce_a_n"    LOC="P7" | IOSTANDARD=LVCMOS33 | SLEW=FAST;   
NET "ub_a_n"    LOC="T4" | IOSTANDARD=LVCMOS33 | SLEW=FAST;   
NET "lb_a_n"    LOC="P6" | IOSTANDARD=LVCMOS33 | SLEW=FAST;   

# sram chip 2 data, ce, ub, lb
NET "dio_b<15>" LOC="N1" | IOSTANDARD=LVCMOS33 | SLEW=FAST;
NET "dio_b<14>" LOC="M1" | IOSTANDARD=LVCMOS33 | SLEW=FAST;
NET "dio_b<13>" LOC="K2" | IOSTANDARD=LVCMOS33 | SLEW=FAST;
NET "dio_b<12>" LOC="C3" | IOSTANDARD=LVCMOS33 | SLEW=FAST;
NET "dio_b<11>" LOC="F5" | IOSTANDARD=LVCMOS33 | SLEW=FAST;
NET "dio_b<10>" LOC="G1" | IOSTANDARD=LVCMOS33 | SLEW=FAST;
NET "dio_b<9>"  LOC="E2" | IOSTANDARD=LVCMOS33 | SLEW=FAST;
NET "dio_b<8>"  LOC="D2" | IOSTANDARD=LVCMOS33 | SLEW=FAST;
NET "dio_b<7>"  LOC="D1" | IOSTANDARD=LVCMOS33 | SLEW=FAST;
NET "dio_b<6>"  LOC="E1" | IOSTANDARD=LVCMOS33 | SLEW=FAST;
NET "dio_b<5>"  LOC="G2" | IOSTANDARD=LVCMOS33 | SLEW=FAST;
NET "dio_b<4>"  LOC="J1" | IOSTANDARD=LVCMOS33 | SLEW=FAST;
NET "dio_b<3>"  LOC="K1" | IOSTANDARD=LVCMOS33 | SLEW=FAST;
NET "dio_b<2>"  LOC="M2" | IOSTANDARD=LVCMOS33 | SLEW=FAST;
NET "dio_b<1>"  LOC="N2" | IOSTANDARD=LVCMOS33 | SLEW=FAST;
NET "dio_b<0>"  LOC="P2" | IOSTANDARD=LVCMOS33 | SLEW=FAST;
NET "ce_b_n"    LOC="N5" | IOSTANDARD=LVCMOS33 | SLEW=FAST; 
NET "ub_b_n"    LOC="R4" | IOSTANDARD=LVCMOS33 | SLEW=FAST; 
NET "lb_b_n"    LOC="P5" | IOSTANDARD=LVCMOS33 | SLEW=FAST; 

#========================================================
# Timing constraint of S3 50-MHz onboard oscillator
# name of the clock signal is clk
#========================================================
NET "clk" TNM_NET = "clk";
TIMESPEC "TS_clk" = PERIOD "clk" 20 ns HIGH 50 %;