regkeys

This code is a FIFO memory vhdl developed in ISE Software

s
prop_308_name
PROP_ModelSimSignalWin
s
prop_308_val
"true"
s
prop_309_name
PROP_ModelSimWaveWin
s
prop_309_val
"true"
s
prop_30_name
PROP_SimUseCustom_postMap
s
prop_30_val
"false"
s
prop_310_name
PROP_ModelSimStructWin
s
prop_310_val
"true"
s
prop_311_name
PROP_ModelSimSourceWin
s
prop_311_val
"false"
s
prop_312_name
PROP_ModelSimListWin
s
prop_312_val
"false"
s
prop_313_name
PROP_ModelSimVarsWin
s
prop_313_val
"false"
s
prop_314_name
PROP_ModelSimProcWin
s
prop_314_val
"false"
s
prop_315_name
PROP_ModelSimDataWin
s
prop_315_val
"false"
s
prop_316_name
PROP_ModelSimSimRes
s
prop_316_val
"Default (1 ps)"
s
prop_317_name
PROP_SimSyntax
s
prop_317_val
"93"
s
prop_318_name
PROP_SimUseExpDeclOnly
s
prop_318_val
"true"
s
prop_319_name
PROP_ModelSimSimRunTime_tb
s
prop_319_val
"1000ns"
s
prop_31_name
PROP_SimUseCustom_postPar
s
prop_31_val
"false"
s
prop_320_name
PROP_ModelSimUutInstName_postMap
s
prop_320_val
"UUT"
s
prop_321_name
PROP_ModelSimUutInstName_postPar
s
prop_321_val
"UUT"
s
prop_322_name
PROP_ModelSimUutInstName_postFit
s
prop_322_val
"UUT"
s
prop_323_name
PROP_SimGenVcdFile
s
prop_323_val
"false"
s
prop_324_name
PROP_SimCustom_launchMSim
s
prop_324_val
""
s
prop_325_name
PROP_SimCustom_behav
s
prop_325_val
""
s
prop_326_name
PROP_SimCustom_postXlate
s
prop_326_val
""
s
prop_327_name
PROP_SimCustom_postMap
s
prop_327_val
""
s
prop_328_name
PROP_SimCustom_postPar
s
prop_328_val
""
s
prop_329_name
PROP_ModelSimSimRunTime_tbw
s
prop_329_val
"1000ns"
s
prop_32_name
PROP_ModelSimUseConfigName
s
prop_32_val
"false"
s
prop_330_name
PROP_ModelSimConfigName
s
prop_330_val
"Default"
s
prop_331_name
PROP_SimModelRenTopLevInstTo
s
prop_331_val
"UUT"
s
prop_332_name
PROP_SynthConstraintsFile
s
prop_332_val
""
s
prop_333_name
PROP_ISimCustomSimCmdFileName_par_tb
s
prop_333_val
""
s
prop_334_name
PROP_ISimCustomSimCmdFileName_par_tbw
s
prop_334_val
""
s
prop_335_name
PROP_ISimCustomSimCmdFileName_behav_tb
s
prop_335_val
""
s
prop_336_name
PROP_ISimCustomSimCmdFileName_behav_tbw
s
prop_336_val
""
s
prop_337_name
PROP_ISimCustomSimCmdFileName_gen_tbw
s
prop_337_val
""
s
prop_338_name
PROP_ISimCustomSimCmdFileName_launch
s
prop_338_val
""
s
prop_339_name
PROP_ISimSimulationRun_par_tb
s
prop_339_val
"true"
s
prop_33_name
PROP_MSimSDFTimingToBeRead
s
prop_33_val
"Setup Time"
s
prop_340_name
PROP_ISimSimulationRun_par_tbw
s
prop_340_val
"true"
s
prop_341_name
PROP_ISimSimulationRun_behav_tb
s
prop_341_val
"true"
s
prop_342_name
PROP_ISimSimulationRun_behav_tbw
s
prop_342_val
"true"
s
prop_343_name
PROP_ISimGenVCDFile_par_tb
s
prop_343_val
"false"
s
prop_344_name
PROP_ISimGenVCDFile_par_tbw
s
prop_344_val
"false"
s
prop_345_name
PROP_ISimCustomCompilationOrderFile
s
prop_345_val
""
s
prop_346_name
PROP_impactBaud
s
prop_346_val
"None"
s
prop_347_name
PROP_impactPort
s
prop_347_val
"Auto - default"
s
prop_348_name
PROP_XPowerOptAdvancedVerboseRpt
s
prop_348_val
"false"
s
prop_349_name
PROP_XPowerOptMaxNumberLines
s
prop_349_val
"1000"
s
prop_34_name
PROP_OverwriteSym
s
prop_34_val
"false"
s
prop_350_name
PROP_xstSafeImplement
s
prop_350_val
"No"
s
prop_351_name
PROP_XplorerRunType
s
prop_351_val
"Yes"
s
prop_352_name
PROP_XplorerNumIterations
s
prop_352_val
"7"
s
prop_353_name
PROP_XplorerEnableRetiming
s
prop_353_val
"true"
s
prop_354_name
PROP_XplorerWarnToBackup
s
prop_354_val
"true"
s
prop_355_name
PROP_XplorerOtherCmdLineOptions
s
prop_355_val
""
s
prop_356_name
PROP_PrecNumOfSumPaths
s
prop_356_val
"10"
s
prop_357_name
PROP_PrecNumOfCriticalPaths
s
prop_357_val
"1"
s
prop_358_name
PROP_mapTimingMode
s
prop_358_val
"Non Timing Driven"
s
prop_359_name
PROP_xilxMapPackfactor
s
prop_359_val
"100"
s
prop_35_name
PROP_CompxlibOutputDir
s
prop_35_val
"$XILINX/<language>/<simulator>"
s
prop_360_name
PROP_MapRetiming
s
prop_360_val
"false"
s
prop_361_name
PROP_MapEquivalentRegisterRemoval
s
prop_361_val
"true"
s
prop_362_name
PROP_xilxPAReffortLevel
s
prop_362_val
"Standard"
s
prop_363_name
PROP_parTimingMode
s
prop_363_val
"Performance Evaluation"
s
prop_364_name
PROP_parGenAsyDlyRpt
s
prop_364_val
"false"
s
prop_365_name
PROP_parGenClkRegionRpt
s
prop_365_val
"false"
s
prop_366_name
PROP_parGenTimingRpt
s
prop_366_val
"true"
s
prop_367_name
PROP_parGenSimModel
s
prop_367_val
"false"
s
prop_368_name
PROP_parPowerReduction
s
prop_368_val
"false"
s
prop_369_name
PROP_mpprViewParRptForSelRslt
s
prop_369_val
""
s
prop_36_name
PROP_CompxlibOverwriteLib
s
prop_36_val
"Overwrite"
s
prop_370_name
PROP_mpprViewPadRptForSelRslt
s
prop_370_val
""
s
prop_371_name
PROP_parMpprParIterations
s
prop_371_val
"3"
s
prop_372_name
PROP_parMpprResultsToSave
s
prop_372_val
""
s
prop_373_name
PROP_parMpprResultsDirectory
s
prop_373_val
""
s
prop_374_name
PROP_parMpprNodelistFile
s
prop_374_val
""
s
prop_375_name
PROP_xilxBitgCfg_GenOpt_DbgBitStr
s
prop_375_val
"false"
s
prop_376_name
PROP_xilxBitgReadBk_GenBitStr
s
prop_376_val
"false"
s
prop_377_name
PROP_xilxBitgCfg_GenOpt_LogicAllocFile
s
prop_377_val
"false"
s
prop_378_name
PROP_xilxBitgCfg_GenOpt_MaskFile
s
prop_378_val
"false"
s
prop_379_name
PROP_SynthRAMStyle
s
prop_379_val
"Auto"
s
prop_37_name
PROP_CompxlibOtherCompxlibOpts
s
prop_37_val
""
s
prop_380_name
PROP_xstROMStyle
s
prop_380_val
"Auto"
s
prop_381_name
PROP_SynthMuxStyle
s
prop_381_val
"Auto"
s
prop_382_name
PROP_xstMoveFirstFfStage
s
prop_382_val
"true"
s
prop_383_name
PROP_xstMoveLastFfStage
s
prop_383_val
"true"
s
prop_384_name
PROP_mapSmartGuideFileName
s
prop_384_val
""
s
prop_385_name
PROP_parSmartGuideFileName
s
prop_385_val
""
s
prop_386_name
PROP_MapPowerReduction
s
prop_386_val
"false"
s
prop_387_name
PROPEXT_SynthFrequencySyn_virtex
s
prop_387_val
"0.0"
s
prop_388_name
PROP_MapEffortLevel
s
prop_388_val
"Medium"
s
prop_389_name
PROP_bitgen_Encrypt_Encrypt
s
prop_389_val
"false"
s
prop_38_name
PROP_CompxlibSimPrimatives
s
prop_38_val
"true"
s
prop_390_name
PROP_MapPlacerCostTable
s
prop_390_val
"1"
s
prop_391_name
PROP_MapLogicOptimization
s
prop_391_val
"false"
s
prop_392_name
PROP_MapRegDuplication
s
prop_392_val
"false"
s
prop_393_name
PROP_DevFamilyPMName
s
prop_393_val
"spartan3e"
s
prop_394_name
PROP_DevDevice
s
prop_394_val
"xc3s100e"
s
prop_395_name
PROP_CompxlibSimPath
s
prop_395_val
"C:/Modeltech_6.2k/win32"
s
prop_396_name
PROP_CompxlibLang
s
prop_396_val
"All"
s
prop_397_name
PROP_SimModelGenMultiHierFile
s
prop_397_val
"false"
s
prop_398_name
PROP_ISimSimulationRunTime_par_tb
s
prop_398_val
"1000 ns"
s
prop_399_name
PROP_ISimSimulationRunTime_par_tbw
s
prop_399_val
"1000 ns"
s
prop_39_name
PROP_XPORTInpFileName
s
prop_39_val
""
s
prop_3_name
PROP_StopImpView
s
prop_3_val
"AbstractSynthesis"
s
prop_400_name
PROP_ISimSimulationRunTime_behav_tb
s
prop_400_val
"1000 ns"
s
prop_401_name
PROP_ISimSimulationRunTime_behav_tbw
s
prop_401_val
"1000 ns"
s
prop_402_name
PROP_ISimVCDFileName_par_tb
s
prop_402_val
"xpower.vcd"
s
prop_403_name
PROP_ISimVCDFileName_par_tbw
s
prop_403_val
"xpower.vcd"
s
prop_404_name
PROP_xilxPARextraEffortLevel
s
prop_404_val
"None"
s
prop_405_name
PROP_parPowerActivityFile
s
prop_405_val
""
s
prop_406_name
PROP_CompxlibSmartModels
s
prop_406_val
"true"
s
prop_407_name
PROP_CompxlibUpdateIniForSmartModel
s
prop_407_val
"false"
s
prop_408_name
PROP_MapPowerActivityFile
s
prop_408_val
""
s
prop_409_name
PROP_bitgen_Encrypt_key0
s
prop_409_val
""
s
prop_40_name
PROP_XPORTInpFileType
s
prop_40_val
"ABEL"
s
prop_410_name
PROP_bitgen_Encrypt_key1
s
prop_410_val
""
s
prop_411_name
PROP_bitgen_Encrypt_key2
s
prop_411_val
""
s
prop_412_name
PROP_bitgen_Encrypt_key3
s
prop_412_val
""
s
prop_413_name
PROP_bitgen_Encrypt_key4
s
prop_413_val
""
s
prop_414_name
PROP_bitgen_Encrypt_key5
s
prop_414_val
""
s
prop_415_name
PROP_bitgen_Encrypt_keyFile
s
prop_415_val
""
s
prop_416_name
PROP_MapExtraEffort
s
prop_416_val
"None"
s
prop_417_name
PROP_xilxBitgCfg_GenOpt_ReadBack_virtex2
s
prop_417_val
"false"
s
prop_418_name
PROP_DevPackage
s
prop_418_val
"vq100"
s
prop_419_name
PROP_Synthesis_Tool
s
prop_419_val
"XST (VHDL/Verilog)"
s
prop_41_name
PROP_XPORTOutFileType
s
prop_41_val
"VHDL"
s
prop_420_name
PROP_CompxlibUniSimLib
s
prop_420_val
"true"
s
prop_421_name
PROP_xilxBitgReadBk_GenBitStr_virtex2
s
prop_421_val
"false"
s
prop_422_name
PROP_xilxBitgCfg_GenOpt_LogicAllocFile_virtex2
s
prop_422_val
"false"
s
prop_423_name
PROP_xilxBitgCfg_GenOpt_MaskFile_virtex2
s
prop_423_val
"false"
s
prop_424_name
PROP_DevSpeed
s
prop_424_val
"-5"
s
prop_425_name
PROP_PreferredLanguage
s
prop_425_val
"VHDL"
s
prop_426_name
PROP_HdlTemplateLang
s
prop_426_val
"VHDL"
s
prop_427_name
PROP_schFuncModelTargetLang
s
prop_427_val
"VHDL"
s
prop_428_name
PROP_schInstTempTargetLang
s
prop_428_val
"VHDL"
s
prop_429_name
PROP_hdlInstTempTargetLang
s
prop_429_val
"VHDL"
s
prop_42_name
PROP_XPORTlistInpFiles
s
prop_42_val
"false"
s
prop_430_name
PROP_ChangeDevSpeed
s
prop_430_val
"-5"
s
prop_431_name
PROP_SimModelTarget
s
prop_431_val
"VHDL"
s
prop_432_name
PROP_xawHdlSourceTargetLang
s
prop_432_val
"VHDL"
s
prop_433_name
PROP_tbwTestbenchTargetLang
s
prop_433_val
"VHDL"
s
prop_434_name
PROP_coregenFuncModelTargetLang
s
prop_434_val
"VHDL"
s
prop_435_name
PROP_xmpInstTempTargetLang
s
prop_435_val
"VHDL"
s
prop_436_name
PROP_sysgenInstTempTargetLang
s
prop_436_val
"VHDL"
s
prop_437_name
PROP_xilxPreTrceSpeed
s
prop_437_val
"-5"
s
prop_438_name
PROP_xilxPostTrceSpeed
s
prop_438_val
"-5"
s
prop_439_name
PROP_HdlTemplateName
s
prop_439_val
"FIFO.vhd"
s
prop_43_name
PROP_SimModelGenerateTestbenchFile
s
prop_43_val
"false"
s
prop_440_name
PROP_SimModelRenTopLevArchTo
s
prop_440_val
"Structure"
s
prop_441_name
PROP_SimModelGenArchOnly
s
prop_441_val
"false"
s
prop_442_name
PROP_SimModelOutputExtIdent
s
prop_442_val
"false"
s
prop_443_name
PROP_SimModelRenTopLevMod
s
prop_443_val
""
s
prop_444_name
PROP_SimModelIncUselibDirInVerilogFile
s
prop_444_val
"false"
s
prop_445_name
PROP_SimModelIncSdfAnnInVerilogFile
s
prop_445_val
"true"
s
prop_446_name
PROP_SimModelNoEscapeSignal
s
prop_446_val
"false"
s
prop_447_name
PROP_netgenPostXlateSimModelName
s
prop_447_val
"FIFO_translate.vhd"
s
prop_448_name
PROP_netgenPostMapSimModelName
s
prop_448_val
"FIFO_map.vhd"
s
prop_449_name
PROP_netgenPostParSimModelName
s
prop_449_val
"FIFO_timesim.vhd"
s
prop_44_name
PROP_SimModelInsertBuffersPulseSwallow
s
prop_44_val
"false"
s
prop_450_name
PROP_bencherPostXlateTestbenchName
s
prop_450_val
"FIFOTB_vhd.translate_vhw"
s
prop_451_name
PROP_bencherPostMapTestbenchName
s
prop_451_val
"FIFOTB_vhd.map_vhw"
s
prop_452_name
PROP_bencherPostParTestbenchName
s
prop_452_val
"FIFOTB_vhd.timesim_vhw"
s
prop_453_name
PROP_SimModelIncSimprimInVerilogFile
s
prop_453_val
"false"
s
prop_454_name
PROP_SimModelIncUnisimInVerilogFile
s
prop_454_val
"false"
s
prop_455_name
PROP_netgenPostSynthesisSimModelName
s
prop_455_val
"FIFO_synthesis.vhd"
s
prop_456_name
PROP_SimModelAutoInsertGlblModuleInNetlist
s
prop_456_val
"true"
s
prop_457_name
PROP_SimModelBringOutGtsNetAsAPort
s
prop_457_val
"false"
s
prop_458_name
PROP_SimModelBringOutGsrNetAsAPort
s
prop_458_val
"false"
s
prop_459_name
PROP_netgenRenameTopLevEntTo
s
prop_459_val
"FIFO"
s
prop_45_name
PROP_SimModelOtherNetgenOpts
s
prop_45_val
""
s
prop_460_name
PROP_SimModelPathUsedInSdfAnn
s
prop_460_val
"Default"
s
prop_46_name
PROP_SimModelRetainHierarchy
s
prop_46_val
"true"
s
prop_47_name
PROP_CorgenRegenCore
s
prop_47_val
"Under Current Project Setting"
s
prop_48_name
PROP_SynthOpt
s
prop_48_val
"Speed"
s
prop_49_name
PROP_SynthOptEffort
s
prop_49_val
"Normal"
s
prop_4_name
PROP_HierarchicalProjectType
s
prop_4_val
"N/A"
s
prop_50_name
PROP_xstUseSynthConstFile
s
prop_50_val
"true"
s
prop_51_name
PROP_xstLibSearchOrder
s
prop_51_val
""
s
prop_52_name
PROP_xstCase
s
prop_52_val
"Maintain"
s
prop_53_name
PROP_xstWorkDir
s
prop_53_val
"./xst"
s
prop_54_name
PROP_xstIniFile
s
prop_54_val
""
s
prop_55_name
PROP_xstVerilog2001
s
prop_55_val
"true"
s
prop_56_name
PROP_xstVeriIncludeDir_Global
s
prop_56_val
""
s
prop_57_name
PROP_xstUserCompileList
s
prop_57_val
""
s
prop_58_name
PROP_xstGenericsParameters
s
prop_58_val
""
s
prop_59_name
PROP_xstVerilogMacros
s
prop_59_val
""
s
prop_5_name
PROP_ProjectGeneratorType
s
prop_5_val
"ProjNav"
s
prop_60_name
PROP_xst_otherCmdLineOptions
s
prop_60_val
""
s
prop_61_name
PROP_xstGenerateRTLNetlist
s
prop_61_val
"Yes"
s
prop_62_name
PROP_xstHierarchySeparator
s
prop_62_val
"/"
s
prop_63_name
PROP_xstBusDelimiter
s
prop_63_val
"<>"
s
prop_64_name
PROP_SynthFsmEncode
s
prop_64_val
"Auto"
s
prop_65_name
PROP_SynthCaseImplStyle
s
prop_65_val
"None"
s
prop_66_name
PROP_SynthResSharing
s
prop_66_val
"true"
s
prop_67_name
PROP_SynthExtractMux
s
prop_67_val
"Yes"
s
prop_68_name
PROP_xilxSynthAddIObuf
s
prop_68_val
"true"
s
prop_69_name
PROP_xstEquivRegRemoval
s
prop_69_val
"true"
s
prop_6_name
PROP_Parse_Target
s
prop_6_val
"synthesis"
s
prop_70_name
PROP_ISimUutInstName
s
prop_70_val
"UUT"
s
prop_71_name
PROP_ISimUseCustomSimCmdFile_par_tb
s
prop_71_val
"false"
s
prop_72_name
PROP_ISimUseCustomSimCmdFile_par_tbw
s
prop_72_val
"false"
s
prop_73_name
PROP_ISimUseCustomSimCmdFile_behav_tb
s
prop_73_val
"false"
s
prop_74_name
PROP_ISimUseCustomSimCmdFile_behav_tbw
s
prop_74_val
"false"
s
prop_75_name
PROP_ISimUseCustomSimCmdFile_gen_tbw
s
prop_75_val
"false"
s
prop_76_name
PROP_ISimUseCustomSimCmdFile_launch
s
prop_76_val
"false"
s
prop_77_name
PROP_isimIncreCompilation
s
prop_77_val
"true"
s
prop_78_name
PROP_isimCompileForHdlDebug
s
prop_78_val
"true"
s
prop_79_name
PROP_ISimSDFTimingToBeRead
s
prop_79_val
"Setup Time"
s
prop_7_name
PROP_Top_Level_Module_Type
s
prop_7_val
"HDL"
s
prop_80_name
PROP_isimValueRangeCheck
s
prop_80_val
"false"
s
prop_81_name
PROP_isimSpecifySearchDirectory
s
prop_81_val
""
s
prop_82_name
PROP_ISimSpecifySearchDirectoryChkSyntax
s
prop_82_val
""
s
prop_83_name
PROP_isimSpecifyDefMacroAndValue
s
prop_83_val
""
s
prop_84_name
PROP_ISimSpecifyDefMacroAndValueChkSyntax
s
prop_84_val
""
s
prop_85_name
PROP_ISimLibSearchOrderFile
s
prop_85_val
""
s
prop_86_name
PROP_ISimUseCustomCompilationOrder
s
prop_86_val
"false"
s
prop_87_name
PROP_ISimOtherCompilerOptions_behav
s
prop_87_val
""
s
prop_88_name
PROP_ISimOtherCompilerOptions_par
s
prop_88_val
""
s
prop_89_name
PROP_DefaultTBName
s
prop_89_val
"Default"
s
prop_8_name
PROP_SynthTop
s
prop_8_val
"Architecture|FIFO|Behavioral"
s
prop_90_name
PROP_ibiswriterShowAllModels
s
prop_90_val
"false"
s
prop_91_name
PROP_ImpactProjectFile
s
prop_91_val
""
s
prop_92_name
PROP_ngdbuild_otherCmdLineOptions
s
prop_92_val
""
s
prop_93_name
PROP_SynthXORCollapse
s
prop_93_val
"true"
s
prop_94_name
PROP_xilxNgdbld_AUL
s
prop_94_val
"false"
s
prop_95_name
PROP_xilxNgdbldMacro
s
prop_95_val
""
s
prop_96_name
PROP_xilxSynthKeepHierarchy
s
prop_96_val
"No"
s
prop_97_name
PROP_xstNetlistHierarchy
s
prop_97_val
"As Optimized"
s
prop_98_name
PROP_XPowerOptVerboseRpt
s
prop_98_val
"false"
s
prop_99_name
PROP_XPowerOptLoadXMLFile
s
prop_99_val
"Default"
s
prop_9_name
PROP_BehavioralSimTop
s
prop_9_val
"Architecture|FIFOTB_vhd|behavior"
s