regkeys

This code is a FIFO memory vhdl developed in ISE Software

NUM_PROPERTIES
460
s
prop_100_name
PROP_XPowerOptOutputFile
s
prop_100_val
"Default"
s
prop_101_name
PROP_XPowerOptLoadVCDFile
s
prop_101_val
"Default"
s
prop_102_name
PROP_XPowerOptLoadPCFFile
s
prop_102_val
"Default"
s
prop_103_name
PROP_XPowerOptInputTclScript
s
prop_103_val
""
s
prop_104_name
PROP_XPowerOtherXPowerOpts
s
prop_104_val
""
s
prop_105_name
PROP_XplorerMode
s
prop_105_val
"Off"
s
prop_106_name
PROP_UserEditorPreference
s
prop_106_val
"ISE Text Editor"
s
prop_107_name
PROP_UserEditorCustomSetting
s
prop_107_val
""
s
prop_108_name
PROP_UserConstraintEditorPreference
s
prop_108_val
"Constraints Editor"
s
prop_109_name
PROP_FlowDebugLevel
s
prop_109_val
"0"
s
prop_10_name
PROP_PostXlateSimTop
s
prop_10_val
"Architecture|FIFOTB_vhd|behavior"
s
prop_110_name
PROP_FitterReportFormat
s
prop_110_val
"HTML"
s
prop_111_name
PROP_ToolPathModelSim
s
prop_111_val
""
s
prop_112_name
PROP_ToolPathSynplify
s
prop_112_val
""
s
prop_113_name
PROP_ToolPathSynplifyPro
s
prop_113_val
""
s
prop_114_name
PROP_ToolPathPrecision
s
prop_114_val
""
s
prop_115_name
PROP_ToolPathChipscope
s
prop_115_val
""
s
prop_116_name
PROP_Enable_Message_Capture
s
prop_116_val
"true"
s
prop_117_name
PROP_Enable_Message_Filtering
s
prop_117_val
"false"
s
prop_118_name
PROP_Enable_Incremental_Messaging
s
prop_118_val
"false"
s
prop_119_name
PROP_lockPinsUcfFile
s
prop_119_val
""
s
prop_11_name
PROP_PostMapSimTop
s
prop_11_val
"Architecture|FIFOTB_vhd|behavior"
s
prop_120_name
PROP_PrecInputSdcFile
s
prop_120_val
""
s
prop_121_name
PROP_PrecResourceSharing
s
prop_121_val
"true"
s
prop_122_name
PROP_PrecAdvFsmOptimization
s
prop_122_val
"true"
s
prop_123_name
PROP_PrecUseSafeFsm
s
prop_123_val
"false"
s
prop_124_name
PROP_PrecFsmEncoding
s
prop_124_val
"Auto"
s
prop_125_name
PROP_PrecVhdlSyntax
s
prop_125_val
"VHDL 93"
s
prop_126_name
PROP_PrecFullCase
s
prop_126_val
"false"
s
prop_127_name
PROP_PrecParallelCase
s
prop_127_val
"false"
s
prop_128_name
PROP_PrecArrayBoundsCheck
s
prop_128_val
"false"
s
prop_129_name
PROP_PrecAddIOPads
s
prop_129_val
"true"
s
prop_12_name
PROP_PostParSimTop
s
prop_12_val
"Architecture|FIFOTB_vhd|behavior"
s
prop_130_name
PROP_PrecTranSetResetToLatches
s
prop_130_val
"true"
s
prop_131_name
PROP_PrecRunRetiming
s
prop_131_val
"false"
s
prop_132_name
PROP_PrecRptclockFreq
s
prop_132_val
"true"
s
prop_133_name
PROP_PrecRptTimingSummary
s
prop_133_val
"true"
s
prop_134_name
PROP_PrecRptCriticalPaths
s
prop_134_val
"true"
s
prop_135_name
PROP_PrecRptTimingViolations
s
prop_135_val
"true"
s
prop_136_name
PROP_PrecShowNetFanOut
s
prop_136_val
"true"
s
prop_137_name
PROP_PrecShowClockDomainCrossing
s
prop_137_val
"false"
s
prop_138_name
PROP_PrecRptMissingConstraints
s
prop_138_val
"false"
s
prop_139_name
PROP_PrecOutputFileBase
s
prop_139_val
""
s
prop_13_name
PROP_PostSynthSimTop
s
prop_13_val
"Architecture|FIFOTB_vhd|behavior"
s
prop_140_name
PROP_PrecCreateUcfFromRtlConstraints
s
prop_140_val
"false"
s
prop_141_name
PROP_PrecEdif
s
prop_141_val
"true"
s
prop_142_name
PROP_PrecVerilog
s
prop_142_val
"false"
s
prop_143_name
PROP_PrecVhdl
s
prop_143_val
"false"
s
prop_144_name
PROP_SynthUseFsmExplorerData
s
prop_144_val
"false"
s
prop_145_name
PROP_SynthSymbolicFsm
s
prop_145_val
"true"
s
prop_146_name
PROP_SynthResourceSharing
s
prop_146_val
"true"
s
prop_147_name
PROP_SynthNumCriticalPaths
s
prop_147_val
"0"
s
prop_148_name
PROP_SynthNumStartEndPoints
s
prop_148_val
"0"
s
prop_149_name
PROP_WriteVerilogNetlist
s
prop_149_val
"false"
s
prop_14_name
PROP_UseSmartGuide
s
prop_14_val
"false"
s
prop_150_name
PROP_WriteVHDLNetlist
s
prop_150_val
"false"
s
prop_151_name
PROP_WriteVendorConstFile
s
prop_151_val
"true"
s
prop_152_name
PROP_SynthDisableIOInsertion
s
prop_152_val
"false"
s
prop_153_name
PROP_SynthFanout
s
prop_153_val
"100"
s
prop_154_name
PROP_ConstFileName
s
prop_154_val
""
s
prop_155_name
PROP_ConstFileAddOption
s
prop_155_val
"true"
s
prop_156_name
PROP_SynthProcBound
s
prop_156_val
"true"
s
prop_157_name
PROP_SynthEnumEncoding
s
prop_157_val
"default"
s
prop_158_name
PROP_Verilog2001
s
prop_158_val
"true"
s
prop_159_name
PROP_SynthModular
s
prop_159_val
"false"
s
prop_15_name
PROP_PartitionCreateDelete
s
prop_15_val
""
s
prop_160_name
PROP_SynthRetiming
s
prop_160_val
"false"
s
prop_161_name
PROP_SynthPipelining
s
prop_161_val
"true"
s
prop_162_name
PROP_mapIgnoreTimingConstraints
s
prop_162_val
"false"
s
prop_163_name
PROP_mapTimingAnalyzerLoadDesign
s
prop_163_val
"true"
s
prop_164_name
PROP_parTimingAnalyzerLoadDesign
s
prop_164_val
"true"
s
prop_165_name
PROP_ngdbuildUseLOCConstraints
s
prop_165_val
"true"
s
prop_166_name
PROP_xilxNgdbldNTType
s
prop_166_val
"Timestamp"
s
prop_167_name
PROP_xilxNgdbldIOPads
s
prop_167_val
"false"
s
prop_168_name
PROP_xilxNgdbldUnexpBlks
s
prop_168_val
"false"
s
prop_169_name
PROP_xilxNgdbldUR
s
prop_169_val
""
s
prop_16_name
PROP_PartitionForceSynth
s
prop_16_val
""
s
prop_170_name
PROP_xilxMapTrimUnconnSig
s
prop_170_val
"true"
s
prop_171_name
PROP_xilxMapReplicateLogic
s
prop_171_val
"true"
s
prop_172_name
PROP_xilxMapAllowLogicOpt
s
prop_172_val
"false"
s
prop_173_name
PROP_xilxMapCoverMode
s
prop_173_val
"Area"
s
prop_174_name
PROP_xilxMapReportDetail
s
prop_174_val
"false"
s
prop_175_name
PROP_mapUseRLOCConstraints
s
prop_175_val
"true"
s
prop_176_name
PROP_xilxMapPackRegInto
s
prop_176_val
"For Inputs and Outputs"
s
prop_177_name
PROP_xilxMapDisableRegOrdering
s
prop_177_val
"false"
s
prop_178_name
PROP_xilxTriStateBuffTXMode
s
prop_178_val
"Off"
s
prop_179_name
PROP_xilxMapSliceLogicInUnusedBRAMs
s
prop_179_val
"false"
s
prop_17_name
PROP_PartitionForceTranslate
s
prop_17_val
""
s
prop_180_name
PROP_MapGlobalOptimization
s
prop_180_val
"false"
s
prop_181_name
PROP_map_otherCmdLineOptions
s
prop_181_val
""
s
prop_182_name
PROP_xilxPARplacerEffortLevel
s
prop_182_val
"None"
s
prop_183_name
PROP_xilxPARrouterEffortLevel
s
prop_183_val
"None"
s
prop_184_name
PROP_xilxPARplacerCostTable
s
prop_184_val
"1"
s
prop_185_name
PROP_xilxPARstrat
s
prop_185_val
"Normal Place and Route"
s
prop_186_name
PROP_parIgnoreTimingConstraints
s
prop_186_val
"false"
s
prop_187_name
PROP_xilxPARuseBondedIO
s
prop_187_val
"false"
s
prop_188_name
PROP_par_otherCmdLineOptions
s
prop_188_val
""
s
prop_189_name
PROP_mpprViewParRptsForAllRslt
s
prop_189_val
"true"
s
prop_18_name
PROP_PartitionForcePlacement
s
prop_18_val
""
s
prop_190_name
PROP_mpprViewPadRptsForAllRslt
s
prop_190_val
"true"
s
prop_191_name
PROP_mpprRsltToCopy
s
prop_191_val
""
s
prop_192_name
PROP_xilxBitgCfg_GenOpt_DRC
s
prop_192_val
"true"
s
prop_193_name
PROP_xilxBitgCfg_GenOpt_BitFile
s
prop_193_val
"true"
s
prop_194_name
PROP_xilxBitgCfg_GenOpt_BinaryFile
s
prop_194_val
"false"
s
prop_195_name
PROP_xilxBitgCfg_GenOpt_ASCIIFile
s
prop_195_val
"false"
s
prop_196_name
PROP_xilxBitgCfg_GenOpt_Compress
s
prop_196_val
"false"
s
prop_197_name
PROP_xilxBitgCfg_GenOpt_GClkDel0
s
prop_197_val
"11111"
s
prop_198_name
PROP_xilxBitgCfg_GenOpt_GClkDel1
s
prop_198_val
"11111"
s
prop_199_name
PROP_xilxBitgCfg_GenOpt_GClkDel2
s
prop_199_val
"11111"
s
prop_19_name
PROP_DesignName
s
prop_19_val
"FIFO"
s
prop_1_name
PROP_SteCreatedBy
s
prop_1_val
""
s
prop_200_name
PROP_xilxBitgCfg_GenOpt_GClkDel3
s
prop_200_val
"11111"
s
prop_201_name
PROP_bitgen_otherCmdLineOptions
s
prop_201_val
""
s
prop_202_name
PROP_xilxBitgCfg_Clk
s
prop_202_val
"Pull Up"
s
prop_203_name
PROP_xilxBitgCfg_M0
s
prop_203_val
"Pull Up"
s
prop_204_name
PROP_xilxBitgCfg_M1
s
prop_204_val
"Pull Up"
s
prop_205_name
PROP_xilxBitgCfg_M2
s
prop_205_val
"Pull Up"
s
prop_206_name
PROP_xilxBitgCfg_Pgm
s
prop_206_val
"Pull Up"
s
prop_207_name
PROP_xilxBitgCfg_Done
s
prop_207_val
"Pull Up"
s
prop_208_name
PROP_xilxBitgCfg_TCK
s
prop_208_val
"Pull Up"
s
prop_209_name
PROP_xilxBitgCfg_TDI
s
prop_209_val
"Pull Up"
s
prop_20_name
PROP_Dummy
s
prop_20_val
"dum1"
s
prop_210_name
PROP_xilxBitgCfg_TDO
s
prop_210_val
"Pull Up"
s
prop_211_name
PROP_xilxBitgCfg_TMS
s
prop_211_val
"Pull Up"
s
prop_212_name
PROP_xilxBitgCfg_Unused
s
prop_212_val
"Pull Down"
s
prop_213_name
PROP_xilxBitgCfg_Code
s
prop_213_val
"0xFFFFFFFF"
s
prop_214_name
PROP_xilxBitgStart_Clk
s
prop_214_val
"CCLK"
s
prop_215_name
PROP_xilxBitgStart_IntDone
s
prop_215_val
"false"
s
prop_216_name
PROP_xilxBitgStart_Clk_Done
s
prop_216_val
"Default (4)"
s
prop_217_name
PROP_xilxBitgStart_Clk_EnOut
s
prop_217_val
"Default (5)"
s
prop_218_name
PROP_xilxBitgStart_Clk_RelSet
s
prop_218_val
"Default (6)"
s
prop_219_name
PROP_xilxBitgStart_Clk_WrtEn
s
prop_219_val
"Default (6)"
s
prop_21_name
PROP_LastAppliedGoal
s
prop_21_val
"Balanced"
s
prop_220_name
PROP_xilxBitgStart_Clk_RelDLL
s
prop_220_val
"Default (NoWait)"
s
prop_221_name
PROP_xilxBitgStart_Clk_DriveDone
s
prop_221_val
"false"
s
prop_222_name
PROP_xilxBitgReadBk_Sec
s
prop_222_val
"Enable Readback and Reconfiguration"
s
prop_223_name
PROP_xilxBitgCfg_GenOpt_ReadBack
s
prop_223_val
"false"
s
prop_224_name
PROP_CurrentFloorplanFile
s
prop_224_val
""
s
prop_225_name
PROP_xilxPreTrceRpt
s
prop_225_val
"Error Report"
s
prop_226_name
PROP_xilxPreTrceRptLimit
s
prop_226_val
"3"
s
prop_227_name
PROP_xilxPreTrceAdvAna
s
prop_227_val
"false"
s
prop_228_name
PROP_xilxPreTrceUncovPath
s
prop_228_val
""
s
prop_229_name
PROP_xilxPreTrceEndpointPath
s
prop_229_val
""
s
prop_22_name
PROP_LastAppliedStrategy
s
prop_22_val
"Xilinx Default (unlocked)"
s
prop_230_name
PROP_PreTrceFastPath
s
prop_230_val
"false"
s
prop_231_name
PROP_xilxPostTrceRpt
s
prop_231_val
"Verbose Report"
s
prop_232_name
PROP_xilxPostTrceRptLimit
s
prop_232_val
"3"
s
prop_233_name
PROP_xilxPostTrceAdvAna
s
prop_233_val
"false"
s
prop_234_name
PROP_xilxPostTrceUncovPath
s
prop_234_val
""
s
prop_235_name
PROP_xilxPostTrceEndpointPath
s
prop_235_val
""
s
prop_236_name
PROP_PostTrceFastPath
s
prop_236_val
"false"
s
prop_237_name
PROP_xilxPostTrceStamp
s
prop_237_val
""
s
prop_238_name
PROP_PreTrceGenTimegroups
s
prop_238_val
"false"
s
prop_239_name
PROP_PreTrceGenDatasheet
s
prop_239_val
"true"
s
prop_23_name
PROP_LastUnlockStatus
s
prop_23_val
"false"
s
prop_240_name
PROP_PostTrceGenTimegroups
s
prop_240_val
"false"
s
prop_241_name
PROP_PostTrceGenDatasheet
s
prop_241_val
"true"
s
prop_242_name
PROP_xilxPostTrceTSIFile
s
prop_242_val
""
s
prop_243_name
PROP_PreTrceTSIFile
s
prop_243_val
""
s
prop_244_name
PROP_LoadPostTrceTSIFile
s
prop_244_val
"false"
s
prop_245_name
PROP_primetimeBlockRamData
s
prop_245_val
""
s
prop_246_name
PROP_primeFlatternOutputNetlist
s
prop_246_val
"false"
s
prop_247_name
PROP_primeCorrelateOutput
s
prop_247_val
"false"
s
prop_248_name
PROP_primeTopLevelModule
s
prop_248_val
""
s
prop_249_name
PROP_AutoGenFile
s
prop_249_val
"false"
s
prop_24_name
PROP_UserBrowsedStrategyFiles
s
prop_24_val
""
s
prop_250_name
PROP_CompxlibXlnxCoreLib
s
prop_250_val
"true"
s
prop_251_name
PROP_xilxSynthGlobOpt
s
prop_251_val
"AllClockNets"
s
prop_252_name
PROP_xstAutoBRAMPacking
s
prop_252_val
"false"
s
prop_253_name
PROP_xstBRAMUtilRatio
s
prop_253_val
"100"
s
prop_254_name
PROP_xstAsynToSync
s
prop_254_val
"false"
s
prop_255_name
PROP_xstReadCores
s
prop_255_val
"true"
s
prop_256_name
PROP_xstCoresSearchDir
s
prop_256_val
""
s
prop_257_name
PROP_xstWriteTimingConstraints
s
prop_257_val
"false"
s
prop_258_name
PROP_xstSliceUtilRatio
s
prop_258_val
"100"
s
prop_259_name
PROP_xstCrossClockAnalysis
s
prop_259_val
"false"
s
prop_25_name
PROP_SimUseCustom_launchMSim
s
prop_25_val
"false"
s
prop_260_name
PROP_xstFsmStyle
s
prop_260_val
"LUT"
s
prop_261_name
PROP_SynthExtractRAM
s
prop_261_val
"true"
s
prop_262_name
PROP_SynthExtractROM
s
prop_262_val
"true"
s
prop_263_name
PROP_SynthDecoderExtract
s
prop_263_val
"true"
s
prop_264_name
PROP_SynthEncoderExtract
s
prop_264_val
"Yes"
s
prop_265_name
PROP_SynthShiftRegExtract
s
prop_265_val
"true"
s
prop_266_name
PROP_SynthLogicalShifterExtract
s
prop_266_val
"true"
s
prop_267_name
PROP_xilxSynthRegBalancing
s
prop_267_val
"No"
s
prop_268_name
PROP_xstPackIORegister
s
prop_268_val
"Auto"
s
prop_269_name
PROP_xstSlicePacking
s
prop_269_val
"true"
s
prop_26_name
PROP_SimUserCompileList_launchMSim
s
prop_26_val
""
s
prop_270_name
PROP_xstTristate2Logic
s
prop_270_val
"Yes"
s
prop_271_name
PROP_xstOptimizeInsPrimtives
s
prop_271_val
"false"
s
prop_272_name
PROP_xilxSynthRegDuplication
s
prop_272_val
"true"
s
prop_273_name
PROP_xstUseClockEnable
s
prop_273_val
"Yes"
s
prop_274_name
PROP_xstUseSyncSet
s
prop_274_val
"Yes"
s
prop_275_name
PROP_xstUseSyncReset
s
prop_275_val
"Yes"
s
prop_276_name
PROP_VirtexSynthAutoConstrain
s
prop_276_val
"true"
s
prop_277_name
PROP_ibiswriterGeneratePackageParasitics
s
prop_277_val
"false"
s
prop_278_name
PROP_xilxMapTimingDrivenPacking
s
prop_278_val
"false"
s
prop_279_name
PROP_xilxBitgCfg_GenOpt_IEEE1532File
s
prop_279_val
"false"
s
prop_27_name
PROP_SimUseCustom_behav
s
prop_27_val
"false"
s
prop_280_name
PROP_xilxBitgCfg_GenOpt_EnableCRC
s
prop_280_val
"true"
s
prop_281_name
PROP_xilxBitgCfg_PwrDown
s
prop_281_val
"Pull Up"
s
prop_282_name
PROP_xilxBitgCfg_DCMShutdown
s
prop_282_val
"false"
s
prop_283_name
PROP_xilxBitgCfg_DCMBandgap
s
prop_283_val
"false"
s
prop_284_name
PROP_xilxBitgStart_Clk_MatchCycle
s
prop_284_val
"Auto"
s
prop_285_name
PROP_bitgen_Encrypt_keySeq0
s
prop_285_val
"None"
s
prop_286_name
PROP_bitgen_Encrypt_keySeq1
s
prop_286_val
"None"
s
prop_287_name
PROP_bitgen_Encrypt_keySeq2
s
prop_287_val
"None"
s
prop_288_name
PROP_bitgen_Encrypt_keySeq3
s
prop_288_val
"None"
s
prop_289_name
PROP_bitgen_Encrypt_keySeq4
s
prop_289_val
"None"
s
prop_28_name
PROP_SimDo
s
prop_28_val
"true"
s
prop_290_name
PROP_bitgen_Encrypt_keySeq5
s
prop_290_val
"None"
s
prop_291_name
PROP_bitgen_Encrypt_startKey
s
prop_291_val
"None"
s
prop_292_name
PROP_bitgen_Encrypt_startCBC
s
prop_292_val
""
s
prop_293_name
PROPEXT_xilxMapGenInputK_virtex2
s
prop_293_val
"4"
s
prop_294_name
PROPEXT_SynthMultStyle_virtex2
s
prop_294_val
"Auto"
s
prop_295_name
PROPEXT_xilxSynthMaxFanout_virtex2
s
prop_295_val
"500"
s
prop_296_name
PROP_usedsp48
s
prop_296_val
"Auto"
s
prop_297_name
PROP_xstDSPUtilRatio
s
prop_297_val
"100"
s
prop_298_name
PROPEXT_xilxBitgCfg_DCIUpdateMode_spartan3
s
prop_298_val
"As Required"
s
prop_299_name
PROPEXT_xilxSynthAddBufg_spartan3e
s
prop_299_val
"24"
s
prop_29_name
PROP_SimUseCustom_postXlate
s
prop_29_val
"false"
s
prop_2_name
PROP_StartImpView
s
prop_2_val
""
s
prop_300_name
PROPEXT_xilxBitgCfg_Rate_spartan3e
s
prop_300_val
"Default (1)"
s
prop_301_name
PROP_SimUserCompileList_behav
s
prop_301_val
""
s
prop_302_name
PROP_DevFamily
s
prop_302_val
"Spartan3E"
s
prop_303_name
PROP_Simulator
s
prop_303_val
"Modelsim-SE Mixed"
s
prop_304_name
PROP_SmartGuideFileName
s
prop_304_val
"FIFO_guide.ncd"
s
prop_305_name
PROP_vsim_otherCmdLineOptions
s
prop_305_val
""
s
prop_306_name
PROP_vlog_otherCmdLineOptions
s
prop_306_val
""
s
prop_307_name
PROP_vcom_otherCmdLineOptions
s
prop_307_val
""