regkeys

I2C Controller VHDL used to communicate two devices. In general this communication is used to config

s
prop_250_val
""
s
prop_251_name
PROP_SimCustom_postPar
s
prop_251_val
""
s
prop_252_name
PROP_ModelSimSimRunTime_tbw
s
prop_252_val
"1000ns"
s
prop_253_name
PROP_ModelSimConfigName
s
prop_253_val
"Default"
s
prop_254_name
PROP_SimModelRenTopLevInstTo
s
prop_254_val
"UUT"
s
prop_255_name
PROP_SynthConstraintsFile
s
prop_255_val
""
s
prop_256_name
PROP_impactPort
s
prop_256_val
"Auto - default"
s
prop_257_name
PROP_XPowerOptAdvancedVerboseRpt
s
prop_257_val
"false"
s
prop_258_name
PROP_XPowerOptMaxNumberLines
s
prop_258_val
"1000"
s
prop_259_name
PROP_xstSafeImplement
s
prop_259_val
"No"
s
prop_25_name
PROP_SimUseCustom_postMap
s
prop_25_val
"false"
s
prop_260_name
PROP_FitterOptimization_xpla3
s
prop_260_val
"Density"
s
prop_261_name
PROP_xcpldFitDesPtermLmt_xbr
s
prop_261_val
"28"
s
prop_262_name
PROP_xcpldFitDesInReg_xbr
s
prop_262_val
"true"
s
prop_263_name
PROP_mapTimingMode
s
prop_263_val
"Non Timing Driven"
s
prop_264_name
PROP_xilxMapPackfactor
s
prop_264_val
"100"
s
prop_265_name
PROP_xilxPAReffortLevel
s
prop_265_val
"Standard"
s
prop_266_name
PROP_parTimingMode
s
prop_266_val
"Performance Evaluation"
s
prop_267_name
PROP_parGenAsyDlyRpt
s
prop_267_val
"false"
s
prop_268_name
PROP_parGenClkRegionRpt
s
prop_268_val
"false"
s
prop_269_name
PROP_parGenTimingRpt
s
prop_269_val
"true"
s
prop_26_name
PROP_SimUseCustom_postPar
s
prop_26_val
"false"
s
prop_270_name
PROP_parGenSimModel
s
prop_270_val
"false"
s
prop_271_name
PROP_parPowerReduction
s
prop_271_val
"false"
s
prop_272_name
PROP_mpprViewParRptForSelRslt
s
prop_272_val
""
s
prop_273_name
PROP_mpprViewPadRptForSelRslt
s
prop_273_val
""
s
prop_274_name
PROP_parMpprParIterations
s
prop_274_val
"3"
s
prop_275_name
PROP_parMpprResultsToSave
s
prop_275_val
""
s
prop_276_name
PROP_parMpprResultsDirectory
s
prop_276_val
""
s
prop_277_name
PROP_parMpprNodelistFile
s
prop_277_val
""
s
prop_278_name
PROP_xilxBitgCfg_GenOpt_DbgBitStr
s
prop_278_val
"false"
s
prop_279_name
PROP_xilxBitgReadBk_GenBitStr
s
prop_279_val
"false"
s
prop_27_name
PROP_ModelSimUseConfigName
s
prop_27_val
"false"
s
prop_280_name
PROP_xilxBitgCfg_GenOpt_LogicAllocFile
s
prop_280_val
"false"
s
prop_281_name
PROP_xilxBitgCfg_GenOpt_MaskFile
s
prop_281_val
"false"
s
prop_282_name
PROP_SynthRAMStyle
s
prop_282_val
"Auto"
s
prop_283_name
PROP_xstROMStyle
s
prop_283_val
"Auto"
s
prop_284_name
PROP_SynthMuxStyle
s
prop_284_val
"Auto"
s
prop_285_name
PROP_xstMoveFirstFfStage
s
prop_285_val
"true"
s
prop_286_name
PROP_xstMoveLastFfStage
s
prop_286_val
"true"
s
prop_287_name
PROP_MapPowerReduction
s
prop_287_val
"false"
s
prop_288_name
PROP_MapEffortLevel
s
prop_288_val
"Medium"
s
prop_289_name
PROP_MapPlacerCostTable
s
prop_289_val
"1"
s
prop_28_name
PROP_MSimSDFTimingToBeRead
s
prop_28_val
"Setup Time"
s
prop_290_name
PROP_MapLogicOptimization
s
prop_290_val
"false"
s
prop_291_name
PROP_MapRegDuplication
s
prop_291_val
"false"
s
prop_292_name
PROP_DevFamilyPMName
s
prop_292_val
"spartan3e"
s
prop_293_name
PROP_DevDevice
s
prop_293_val
"xc3s500e"
s
prop_294_name
PROP_CompxlibSimPath
s
prop_294_val
"C:/Modeltech_xe_starter/win32xoem"
s
prop_295_name
PROP_CompxlibLang
s
prop_295_val
"VHDL"
s
prop_296_name
PROP_SimModelGenMultiHierFile
s
prop_296_val
"false"
s
prop_297_name
PROP_xilxPARextraEffortLevel
s
prop_297_val
"None"
s
prop_298_name
PROP_parPowerActivityFile
s
prop_298_val
""
s
prop_299_name
PROP_MapPowerActivityFile
s
prop_299_val
""
s
prop_29_name
PROP_CompxlibOutputDir
s
prop_29_val
"$XILINX/<language>/<simulator>"
s
prop_2_name
PROP_Parse_Target
s
prop_2_val
"synthesis"
s
prop_300_name
PROP_MapExtraEffort
s
prop_300_val
"None"
s
prop_301_name
PROP_DevPackage
s
prop_301_val
"fg320"
s
prop_302_name
PROP_Synthesis_Tool
s
prop_302_val
"XST (VHDL/Verilog)"
s
prop_303_name
PROP_CompxlibUniSimLib
s
prop_303_val
"true"
s
prop_304_name
PROP_CompxlibUni9000Lib
s
prop_304_val
"true"
s
prop_305_name
PROP_DevSpeed
s
prop_305_val
"-5"
s
prop_306_name
PROP_PreferredLanguage
s
prop_306_val
"VHDL"
s
prop_307_name
PROP_ChangeDevSpeed
s
prop_307_val
"-5"
s
prop_308_name
PROP_SimModelTarget
s
prop_308_val
"VHDL"
s
prop_309_name
PROP_tbwTestbenchTargetLang
s
prop_309_val
"VHDL"
s
prop_30_name
PROP_CompxlibOverwriteLib
s
prop_30_val
"Overwrite"
s
prop_310_name
PROP_coregenFuncModelTargetLang
s
prop_310_val
"VHDL"
s
prop_311_name
PROP_xilxPreTrceSpeed
s
prop_311_val
"-5"
s
prop_312_name
PROP_xilxPostTrceSpeed
s
prop_312_val
"-5"
s
prop_313_name
PROP_SimModelRenTopLevArchTo
s
prop_313_val
"Structure"
s
prop_314_name
PROP_SimModelGenArchOnly
s
prop_314_val
"false"
s
prop_315_name
PROP_SimModelOutputExtIdent
s
prop_315_val
"false"
s
prop_316_name
PROP_SimModelRenTopLevMod
s
prop_316_val
""
s
prop_317_name
PROP_SimModelIncUselibDirInVerilogFile
s
prop_317_val
"false"
s
prop_318_name
PROP_SimModelIncSdfAnnInVerilogFile
s
prop_318_val
"true"
s
prop_319_name
PROP_SimModelNoEscapeSignal
s
prop_319_val
"false"
s
prop_31_name
PROP_CompxlibOtherCompxlibOpts
s
prop_31_val
""
s
prop_320_name
PROP_netgenPostXlateSimModelName
s
prop_320_val
"i2c_unit_control_translate.vhd"
s
prop_321_name
PROP_netgenPostMapSimModelName
s
prop_321_val
"i2c_unit_control_map.vhd"
s
prop_322_name
PROP_netgenPostParSimModelName
s
prop_322_val
"i2c_unit_control_timesim.vhd"
s
prop_323_name
PROP_bencherPostXlateTestbenchName
s
prop_323_val
"clock_i2c_gen_tb.translate_vhw"
s
prop_324_name
PROP_bencherPostMapTestbenchName
s
prop_324_val
"clock_i2c_gen_tb.map_vhw"
s
prop_325_name
PROP_bencherPostParTestbenchName
s
prop_325_val
"clock_i2c_gen_tb.timesim_vhw"
s
prop_326_name
PROP_SimModelIncSimprimInVerilogFile
s
prop_326_val
"false"
s
prop_327_name
PROP_SimModelIncUnisimInVerilogFile
s
prop_327_val
"false"
s
prop_328_name
PROP_netgenPostSynthesisSimModelName
s
prop_328_val
"i2c_unit_control_synthesis.vhd"
s
prop_329_name
PROP_SimModelAutoInsertGlblModuleInNetlist
s
prop_329_val
"true"
s
prop_32_name
PROP_CompxlibSimPrimatives
s
prop_32_val
"true"
s
prop_330_name
PROP_SimModelBringOutGtsNetAsAPort
s
prop_330_val
"false"
s
prop_331_name
PROP_SimModelBringOutGsrNetAsAPort
s
prop_331_val
"false"
s
prop_332_name
PROP_netgenRenameTopLevEntTo
s
prop_332_val
"i2c_unit_control"
s
prop_333_name
PROP_SimModelPathUsedInSdfAnn
s
prop_333_val
"Default"
s
prop_33_name
PROP_SimModelGenerateTestbenchFile
s
prop_33_val
"false"
s
prop_34_name
PROP_SimModelInsertBuffersPulseSwallow
s
prop_34_val
"false"
s
prop_35_name
PROP_SimModelOtherNetgenOpts
s
prop_35_val
""
s
prop_36_name
PROP_SimModelRetainHierarchy
s
prop_36_val
"true"
s
prop_37_name
PROP_CorgenRegenCore
s
prop_37_val
"Under Current Project Setting"
s
prop_38_name
PROP_SynthOpt
s
prop_38_val
"Speed"
s
prop_39_name
PROP_SynthOptEffort
s
prop_39_val
"Normal"
s
prop_3_name
PROP_Top_Level_Module_Type
s
prop_3_val
"HDL"
s
prop_40_name
PROP_xstUseSynthConstFile
s
prop_40_val
"true"
s
prop_41_name
PROP_xstLibSearchOrder
s
prop_41_val
""
s
prop_42_name
PROP_xstCase
s
prop_42_val
"Maintain"
s
prop_43_name
PROP_xstWorkDir
s
prop_43_val
"./xst"
s
prop_44_name
PROP_xstIniFile
s
prop_44_val
""
s
prop_45_name
PROP_xstVerilog2001
s
prop_45_val
"true"
s
prop_46_name
PROP_xstVeriIncludeDir_Global
s
prop_46_val
""
s
prop_47_name
PROP_xstUserCompileList
s
prop_47_val
""
s
prop_48_name
PROP_xstGenericsParameters
s
prop_48_val
""
s
prop_49_name
PROP_xstVerilogMacros
s
prop_49_val
""
s
prop_4_name
PROP_SynthTop
s
prop_4_val
"Architecture|i2c_unit_control|behavioral"
s
prop_50_name
PROP_xst_otherCmdLineOptions
s
prop_50_val
""
s
prop_51_name
PROP_xstGenerateRTLNetlist
s
prop_51_val
"Yes"
s
prop_52_name
PROP_xstHierarchySeparator
s
prop_52_val
"/"
s
prop_53_name
PROP_xstBusDelimiter
s
prop_53_val
"<>"
s
prop_54_name
PROP_SynthFsmEncode
s
prop_54_val
"Auto"
s
prop_55_name
PROP_SynthCaseImplStyle
s
prop_55_val
"None"
s
prop_56_name
PROP_SynthResSharing
s
prop_56_val
"true"
s
prop_57_name
PROP_SynthExtractMux
s
prop_57_val
"Yes"
s
prop_58_name
PROP_xilxSynthAddIObuf
s
prop_58_val
"true"
s
prop_59_name
PROP_xstEquivRegRemoval
s
prop_59_val
"true"
s
prop_5_name
PROP_BehavioralSimTop
s
prop_5_val
"Architecture|i2c_unit_control_tb|behavior"
s
prop_60_name
PROP_ibiswriterShowAllModels
s
prop_60_val
"false"
s
prop_61_name
PROP_ImpactProjectFile
s
prop_61_val
"Default"
s
prop_62_name
PROP_ngdbuild_otherCmdLineOptions
s
prop_62_val
""
s
prop_63_name
PROP_SynthXORCollapse
s
prop_63_val
"true"
s
prop_64_name
PROP_xilxNgdbld_AUL
s
prop_64_val
"false"
s
prop_65_name
PROP_xilxNgdbldMacro
s
prop_65_val
""
s
prop_66_name
PROP_xilxSynthKeepHierarchy
s
prop_66_val
"No"
s
prop_67_name
PROP_xstNetlistHierarchy
s
prop_67_val
"As Optimized"
s
prop_68_name
PROP_XPowerOptVerboseRpt
s
prop_68_val
"false"
s
prop_69_name
PROP_XPowerOptLoadXMLFile
s
prop_69_val
"Default"
s
prop_6_name
PROP_PostXlateSimTop
s
prop_6_val
"Architecture|clock_i2c_gen_tb|behavior"
s
prop_70_name
PROP_XPowerOptOutputFile
s
prop_70_val
"Default"
s
prop_71_name
PROP_XPowerOptLoadVCDFile
s
prop_71_val
"Default"
s
prop_72_name
PROP_XPowerOptLoadPCFFile
s
prop_72_val
"Default"
s
prop_73_name
PROP_XPowerOptInputTclScript
s
prop_73_val
""
s
prop_74_name
PROP_XPowerOtherXPowerOpts
s
prop_74_val
""
s
prop_75_name
PROP_XplorerMode
s
prop_75_val
"Off"
s
prop_76_name
PROP_UserEditorPreference
s
prop_76_val
"ISE Text Editor"
s
prop_77_name
PROP_UserEditorCustomSetting
s
prop_77_val
""
s
prop_78_name
PROP_UserConstraintEditorPreference
s
prop_78_val
"Constraints Editor"
s
prop_79_name
PROP_FlowDebugLevel
s
prop_79_val
"0"
s
prop_7_name
PROP_PostMapSimTop
s
prop_7_val
"Architecture|clock_i2c_gen_tb|behavior"
s
prop_80_name
PROP_FitterReportFormat
s
prop_80_val
"HTML"
s
prop_81_name
PROP_Enable_Message_Capture
s
prop_81_val
"true"
s
prop_82_name
PROP_Enable_Message_Filtering
s
prop_82_val
"false"
s
prop_83_name
PROP_Enable_Incremental_Messaging
s
prop_83_val
"false"
s
prop_84_name
PROP_lockPinsUcfFile
s
prop_84_val
""
s
prop_85_name
PROP_EnableWYSIWYG
s
prop_85_val
"None"
s
prop_86_name
PROP_xcpldUseLocConst
s
prop_86_val
"Always"
s
prop_87_name
PROP_xcpldFitDesInit
s
prop_87_val
"Low"
s
prop_88_name
PROP_xcpldFitDesTimingCst
s
prop_88_val
"true"
s
prop_89_name
PROP_CPLDFitkeepio
s
prop_89_val
"false"
s
prop_8_name
PROP_PostParSimTop
s
prop_8_val
"Architecture|clock_i2c_gen_tb|behavior"
s
prop_90_name
PROP_cpldBestFit
s
prop_90_val
"false"
s
prop_91_name
PROP_xcpldFitDesMultiLogicOpt
s
prop_91_val
"true"
s
prop_92_name
PROP_cpldfit_otherCmdLineOptions
s
prop_92_val
""
s
prop_93_name
PROP_fitGenSimModel
s
prop_93_val
"false"
s
prop_94_name
PROP_cpldfitHDLeqStyle
s
prop_94_val
"Source"
s
prop_95_name
PROP_xcpldFitDesSlew
s
prop_95_val
"Fast"
s
prop_96_name
PROP_xcpldUseGlobalClocks
s
prop_96_val
"true"
s
prop_97_name
PROP_xcpldUseGlobalOutputEnables
s
prop_97_val
"true"
s
prop_98_name
PROP_xcpldUseGlobalSetReset
s
prop_98_val
"true"
s
prop_99_name
PROP_hprep6_autosig
s
prop_99_val
"false"
s
prop_9_name
PROP_PostFitSimTop
s
prop_9_val
""
s