4bitcomp.vhd

来自「I try 4-bit comparator here in VHDL」· VHDL 代码 · 共 45 行

-- 4bitcomp.vhd
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity a_4_bit_comparator is

port  ( A:  in std_logic_vector(3 downto 0);    -- Nibble A input
        B:  in std_logic_vector(3 downto 0);    -- Nibble B input
        
        A_more_B_in:  in std_logic;    -- A less than B extension input
        A_less_B_in:  in std_logic;    -- A more than B extension input
        A_equal_B_in: in std_logic;    -- A equal to B extension input
        
        A_more_B:     out std_logic;   -- A less than B output
        A_less_B:     out std_logic;   -- A more than B output
        A_equal_B:    out std_logic);  -- A equal to B output

end a_4_bit_comparator;

architecture arch of a_4_bit_comparator is

begin

A_more_B <= '1' when  A(3)>B(3) else
            '1' when (A(3)=B(3) and A(2)>B(2)) else
            '1' when (A(3 downto 2)=B(3 downto 2) and A(1)>B(1)) else
            '1' when (A(3 downto 1)=B(3 downto 1) and A(0)>B(0)) else
            '1' when (A=B and A_more_B_in='1' and A_less_B_in='0' and A_equal_B_in='0') else
            '1' when (A=B and A_more_B_in='0' and A_less_B_in='0' and A_equal_B_in='0') else
            '0';

A_less_B <= '1' when  A(3)<B(3) else
            '1' when (A(3)=B(3) and A(2)<B(2)) else
            '1' when (A(3 downto 2)=B(3 downto 2) and A(1)<B(1)) else
            '1' when (A(3 downto 1)=B(3 downto 1) and A(0)<B(0)) else
            '1' when (A=B and A_more_B_in='0' and A_less_B_in='1' and A_equal_B_in='0') else
            '1' when (A=B and A_more_B_in='0' and A_less_B_in='0' and A_equal_B_in='0') else
            '0';

A_equal_B<= '1' when (A=B and A_equal_B_in='1') else
            '0';

end arch;