modelundertest_tbench.vhd

I try 4-bit comparator here in VHDL

-- Generated by WaveFormer Lite Version 12.15b at 22:4:9 on 11/17/2008
-- Stimulator for stimulus

-- Generation Settings:
--   Export type: Stimulus only (reactive export not enabled)
--                Delays, Samples, Markers, etc will not generate code.

-- Clock Domains:

--   Unclocked
--   ---------
--     Signals:
--       A
--       B

library ieee, std;
use ieee.std_logic_1164.all;
library syncad_vhdl_lib;
use syncad_vhdl_lib.TBDefinitions.all;
-- Additional libraries used by Model Under Test.
library IEEE;
use IEEE.std_logic_arith.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
-- End Additional libraries used by Model Under Test.

entity stimulus is
  port (
    A : inout std_logic_vector(3 downto 0) := x"9";
    B : inout std_logic_vector(3 downto 0) := x"A";
    A_more_B_in : inout std_logic := '0';
    A_less_B_in : inout std_logic := '0';
    A_equal_B_in : inout std_logic := '0');

end stimulus;

architecture STIMULATOR of stimulus is

  -- Control Signal Declarations
  signal tb_status : TStatus;
  signal tb_ParameterInitFlag : boolean := false;

  -- Parm Declarations
  signal A_equal_B_in_MinHL : time := 0 ns;
  signal A_equal_B_in_MaxHL : time := 0 ns;
  signal A_equal_B_in_MinLH : time := 0 ns;
  signal A_equal_B_in_MaxLH : time := 0 ns;
  signal A_equal_B_in_JFall : time := 0 ns;
  signal A_equal_B_in_JRise : time := 0 ns;
  signal A_equal_B_in_Duty : real := 0.0;
  signal A_equal_B_in_Period : time := 0 ns;
  signal A_equal_B_in_Offset : time := 0 ns;
  signal A_less_B_in_MinHL : time := 0 ns;
  signal A_less_B_in_MaxHL : time := 0 ns;
  signal A_less_B_in_MinLH : time := 0 ns;
  signal A_less_B_in_MaxLH : time := 0 ns;
  signal A_less_B_in_JFall : time := 0 ns;
  signal A_less_B_in_JRise : time := 0 ns;
  signal A_less_B_in_Duty : real := 0.0;
  signal A_less_B_in_Period : time := 0 ns;
  signal A_less_B_in_Offset : time := 0 ns;
  signal A_more_B_in_MinHL : time := 0 ns;
  signal A_more_B_in_MaxHL : time := 0 ns;
  signal A_more_B_in_MinLH : time := 0 ns;
  signal A_more_B_in_MaxLH : time := 0 ns;
  signal A_more_B_in_JFall : time := 0 ns;
  signal A_more_B_in_JRise : time := 0 ns;
  signal A_more_B_in_Duty : real := 0.0;
  signal A_more_B_in_Period : time := 0 ns;
  signal A_more_B_in_Offset : time := 0 ns;

  -- Status Control block.

begin

  process
    variable good : boolean;
  begin
    wait until tb_ParameterInitFlag;
    tb_status <= TB_ONCE;
    wait for 250 ns;
    tb_status <= TB_DONE;
    wait;
  end process;

  -- Parm Assignment Block
  AssignParms : process
    variable A_equal_B_in_MinHL_real : real;
    variable A_equal_B_in_MaxHL_real : real;
    variable A_equal_B_in_MinLH_real : real;
    variable A_equal_B_in_MaxLH_real : real;
    variable A_equal_B_in_JFall_real : real;
    variable A_equal_B_in_JRise_real : real;
    variable A_equal_B_in_Duty_real : real;
    variable A_equal_B_in_Period_real : real;
    variable A_equal_B_in_Offset_real : real;
    variable A_less_B_in_MinHL_real : real;
    variable A_less_B_in_MaxHL_real : real;
    variable A_less_B_in_MinLH_real : real;
    variable A_less_B_in_MaxLH_real : real;
    variable A_less_B_in_JFall_real : real;
    variable A_less_B_in_JRise_real : real;
    variable A_less_B_in_Duty_real : real;
    variable A_less_B_in_Period_real : real;
    variable A_less_B_in_Offset_real : real;
    variable A_more_B_in_MinHL_real : real;
    variable A_more_B_in_MaxHL_real : real;
    variable A_more_B_in_MinLH_real : real;
    variable A_more_B_in_MaxLH_real : real;
    variable A_more_B_in_JFall_real : real;
    variable A_more_B_in_JRise_real : real;
    variable A_more_B_in_Duty_real : real;
    variable A_more_B_in_Period_real : real;
    variable A_more_B_in_Offset_real : real;
  begin
    A_equal_B_in_MinHL_real := 0.0;
    A_equal_B_in_MinHL <= A_equal_B_in_MinHL_real * 1 ns;
    A_equal_B_in_MaxHL_real := 0.0;
    A_equal_B_in_MaxHL <= A_equal_B_in_MaxHL_real * 1 ns;
    A_equal_B_in_MinLH_real := 0.0;
    A_equal_B_in_MinLH <= A_equal_B_in_MinLH_real * 1 ns;
    A_equal_B_in_MaxLH_real := 0.0;
    A_equal_B_in_MaxLH <= A_equal_B_in_MaxLH_real * 1 ns;
    A_equal_B_in_JFall_real := 0.0;
    A_equal_B_in_JFall <= A_equal_B_in_JFall_real * 1 ns;
    A_equal_B_in_JRise_real := 0.0;
    A_equal_B_in_JRise <= A_equal_B_in_JRise_real * 1 ns;
    A_equal_B_in_Duty_real := 50.0;
    A_equal_B_in_Duty <= A_equal_B_in_Duty_real;
    A_equal_B_in_Period_real := 75.0;
    A_equal_B_in_Period <= A_equal_B_in_Period_real * 1 ns;
    A_equal_B_in_Offset_real := 0.0;
    A_equal_B_in_Offset <= A_equal_B_in_Offset_real * 1 ns;
    A_less_B_in_MinHL_real := 0.0;
    A_less_B_in_MinHL <= A_less_B_in_MinHL_real * 1 ns;
    A_less_B_in_MaxHL_real := 0.0;
    A_less_B_in_MaxHL <= A_less_B_in_MaxHL_real * 1 ns;
    A_less_B_in_MinLH_real := 0.0;
    A_less_B_in_MinLH <= A_less_B_in_MinLH_real * 1 ns;
    A_less_B_in_MaxLH_real := 0.0;
    A_less_B_in_MaxLH <= A_less_B_in_MaxLH_real * 1 ns;
    A_less_B_in_JFall_real := 0.0;
    A_less_B_in_JFall <= A_less_B_in_JFall_real * 1 ns;
    A_less_B_in_JRise_real := 0.0;
    A_less_B_in_JRise <= A_less_B_in_JRise_real * 1 ns;
    A_less_B_in_Duty_real := 50.0;
    A_less_B_in_Duty <= A_less_B_in_Duty_real;
    A_less_B_in_Period_real := 100.0;
    A_less_B_in_Period <= A_less_B_in_Period_real * 1 ns;
    A_less_B_in_Offset_real := 0.0;
    A_less_B_in_Offset <= A_less_B_in_Offset_real * 1 ns;
    A_more_B_in_MinHL_real := 0.0;
    A_more_B_in_MinHL <= A_more_B_in_MinHL_real * 1 ns;
    A_more_B_in_MaxHL_real := 0.0;
    A_more_B_in_MaxHL <= A_more_B_in_MaxHL_real * 1 ns;
    A_more_B_in_MinLH_real := 0.0;
    A_more_B_in_MinLH <= A_more_B_in_MinLH_real * 1 ns;
    A_more_B_in_MaxLH_real := 0.0;
    A_more_B_in_MaxLH <= A_more_B_in_MaxLH_real * 1 ns;
    A_more_B_in_JFall_real := 0.0;
    A_more_B_in_JFall <= A_more_B_in_JFall_real * 1 ns;
    A_more_B_in_JRise_real := 0.0;
    A_more_B_in_JRise <= A_more_B_in_JRise_real * 1 ns;
    A_more_B_in_Duty_real := 50.0;
    A_more_B_in_Duty <= A_more_B_in_Duty_real;
    A_more_B_in_Period_real := 50.0;
    A_more_B_in_Period <= A_more_B_in_Period_real * 1 ns;
    A_more_B_in_Offset_real := 0.0;
    A_more_B_in_Offset <= A_more_B_in_Offset_real * 1 ns;
    tb_ParameterInitFlag <= true;
    wait;
  end process;

  -- Clocks

  -- Clock Instantiation
  tb_A_more_B_in : entity syncad_vhdl_lib.tb_clock_minmax
    generic map (name => "tb_A_more_B_in",
                initialize => true,
                state1 => '1',
                state2 => '0')
    port map (tb_status,
              A_more_B_in,
              A_more_B_in_MinLH,
              A_more_B_in_MaxLH,
              A_more_B_in_MinHL,
              A_more_B_in_MaxHL,
              A_more_B_in_Offset,
              A_more_B_in_Period,
              A_more_B_in_Duty,
              A_more_B_in_JRise,
              A_more_B_in_JFall);

  -- Clock Instantiation
  tb_A_less_B_in : entity syncad_vhdl_lib.tb_clock_minmax
    generic map (name => "tb_A_less_B_in",
                initialize => true,
                state1 => '1',
                state2 => '0')
    port map (tb_status,
              A_less_B_in,
              A_less_B_in_MinLH,
              A_less_B_in_MaxLH,
              A_less_B_in_MinHL,
              A_less_B_in_MaxHL,
              A_less_B_in_Offset,
              A_less_B_in_Period,
              A_less_B_in_Duty,
              A_less_B_in_JRise,
              A_less_B_in_JFall);

  -- Clock Instantiation
  tb_A_equal_B_in : entity syncad_vhdl_lib.tb_clock_minmax
    generic map (name => "tb_A_equal_B_in",
                initialize => true,
                state1 => '1',
                state2 => '0')
    port map (tb_status,
              A_equal_B_in,
              A_equal_B_in_MinLH,
              A_equal_B_in_MaxLH,
              A_equal_B_in_MinHL,
              A_equal_B_in_MaxHL,
              A_equal_B_in_Offset,
              A_equal_B_in_Period,
              A_equal_B_in_Duty,
              A_equal_B_in_JRise,
              A_equal_B_in_JFall);

  -- Clocked Sequences

  -- Sequence: Unclocked
  Unclocked : process
  begin
    wait for 50 ns;
    A <= x"B";
    B <= x"8";
    wait for 50 ns;
    A <= x"C";
    B <= x"9";
    wait for 50 ns;
    A <= x"A";
    B <= x"A";
    wait for 50 ns;
    A <= x"F";
    B <= x"E";
    wait for 50 ns;
    wait;
  end process;
end STIMULATOR;

-- Test Bench wrapper for stimulus and Model Under Test
library ieee, std;
use ieee.std_logic_1164.all;
library syncad_vhdl_lib;
use syncad_vhdl_lib.TBDefinitions.all;
-- Additional libraries used by Model Under Test.
library IEEE;
use IEEE.std_logic_arith.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
-- End Additional libraries used by Model Under Test.

entity testbench is
end testbench;
architecture tbGeneratedCode of testbench is
  signal A : std_logic_vector(3 downto 0);
  signal B : std_logic_vector(3 downto 0);
  signal A_more_B_in : std_logic;
  signal A_less_B_in : std_logic;
  signal A_equal_B_in : std_logic;
  signal A_more_B : std_logic;
  signal A_less_B : std_logic;
  signal A_equal_B : std_logic;

  -- Stimulator instance

begin

  stimulus_0 : entity work.stimulus
    port map (A => A,
              B => B,
              A_more_B_in => A_more_B_in,
              A_less_B_in => A_less_B_in,
              A_equal_B_in => A_equal_B_in);

  -- Instantiation of Model Under Test.
  a_4_bit_comparator_0 : entity work.a_4_bit_comparator
    port map (A => A,
              B => B,
              A_more_B_in => A_more_B_in,
              A_less_B_in => A_less_B_in,
              A_equal_B_in => A_equal_B_in,
              A_more_B => A_more_B,
              A_less_B => A_less_B,
              A_equal_B => A_equal_B);
end tbGeneratedCode;