crc_8.vhd

用vhdl编写的CRC校验代码

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity crc_8 is
port(clk :in std_logic ;
     info: in std_logic_vector(10 downto 1);
     crc : out std_logic_vector(8 downto 1);
     sign : out std_logic);
end crc_8;
architecture behav of crc_8 is
signal q:std_logic_vector(18 downto 1);
constant g:std_logic_vector(9 downto 1):="100110001";
begin
process(clk)
variable count:integer;
begin
q(18 downto 9)<=info;
q(8 downto 1)<="00000000";
count:=conv_integer(q);
count:=count mod conv_integer(g);
crc<=conv_std_logic_vector(count,8);
end process;
end behav;