fadd_v.vhd

来自「CPLD VHDL 数码管程序 流水灯程序 时钟程序CPLD VHDL 数码管程」· VHDL 代码 · 共 17 行

LIBRARY ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
ENTITY fadd_v IS
		PORT(A,B,Ci	: IN	STD_LOGIC;
			 S,Co	: OUT	STD_LOGIC);
END fadd_v;

architecture a of fadd_v is
	signal temp: std_logic_vector(1 downto 0);
	begin
		temp <= ('0'& A)+ B+ Ci;
		s <=temp(0);
		Co<=temp(1);
	end a;