count10_v.rpt

CPLD VHDL 数码管程序 流水灯程序 时钟程序CPLD VHDL 数码管程序 流水灯程序 时钟程序

  36     22    B     OUTPUT      t        0      0   0    1    2    0    0  Co
  37     21    B         FF   +  t        1      0   1    5    1    5    0  Q0 (:18)
  39     19    B         FF   +  t        2      0   1    5    4    3    0  Q1 (:17)
  40     18    B         FF   +  t        1      0   1    5    3    3    0  Q2 (:16)
  41     17    B         FF   +  t        3      0   1    5    4    3    0  Q3 (:15)


Code:

s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell


Device-Specific Information:d:\source\aaaaaa\sourcecode\cpld\count_vhdl\count10_v.rpt
count10_v

** LOGIC CELL INTERCONNECTIONS **

Logic Array Block 'B':

                   Logic cells placed in LAB 'B'
        +--------- LC22 Co
        | +------- LC21 Q0
        | | +----- LC19 Q1
        | | | +--- LC18 Q2
        | | | | +- LC17 Q3
        | | | | | 
        | | | | |   Other LABs fed by signals
        | | | | |   that feed LAB 'B'
LC      | | | | | | A B |     Logic cells that feed LAB 'B':
LC21 -> * * * * * | - * | <-- Q0
LC19 -> - - * * * | - * | <-- Q1
LC18 -> - - * * * | - * | <-- Q2
LC17 -> * - * - * | - * | <-- Q3

Pin
43   -> - - - - - | - - | <-- Clk
14   -> - * * * * | - * | <-- Clrn
12   -> - * - - - | - * | <-- D0
11   -> - - * - - | - * | <-- D1
9    -> - - - * - | - * | <-- D2
8    -> - - - - * | - * | <-- D3
6    -> - * * * * | - * | <-- Enp
5    -> * * * * * | - * | <-- Ent
4    -> - * * * * | - * | <-- Load


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:d:\source\aaaaaa\sourcecode\cpld\count_vhdl\count10_v.rpt
count10_v

** EQUATIONS **

Clk      : INPUT;
Clrn     : INPUT;
D0       : INPUT;
D1       : INPUT;
D2       : INPUT;
D3       : INPUT;
Enp      : INPUT;
Ent      : INPUT;
Load     : INPUT;

-- Node name is 'Co' 
-- Equation name is 'Co', location is LC022, type is output.
 Co      = LCELL( _EQ001 $  GND);
  _EQ001 =  Ent &  Q0 &  Q3;

-- Node name is 'Q0' = 'tmp0' 
-- Equation name is 'Q0', location is LC021, type is output.
 Q0      = DFFE( _EQ002 $  Clrn, GLOBAL( Clk),  VCC,  VCC,  VCC);
  _EQ002 =  Clrn &  Enp &  Ent &  Load &  Q0
         #  Clrn & !Enp &  Load & !Q0
         #  Clrn & !Ent &  Load & !Q0
         #  Clrn & !D0 & !Load;

-- Node name is 'Q1' = 'tmp1' 
-- Equation name is 'Q1', location is LC019, type is output.
 Q1      = DFFE( _EQ003 $  Clrn, GLOBAL( Clk),  VCC,  VCC,  VCC);
  _EQ003 =  Clrn &  Enp &  Ent &  Load &  Q0 &  Q1
         #  Clrn &  Load & !Q1 & !Q2 &  Q3
         #  Clrn &  Load & !Q1 &  _X001
         #  Clrn & !D1 & !Load;
  _X001  = EXP( Enp &  Ent &  Q0);

-- Node name is 'Q2' = 'tmp2' 
-- Equation name is 'Q2', location is LC018, type is output.
 Q2      = TFFE( _EQ004, GLOBAL( Clk),  VCC,  VCC,  VCC);
  _EQ004 =  Clrn &  Enp &  Ent &  Load &  Q0 &  Q1 & !Q2
         #  Enp &  Ent &  Load &  Q0 &  Q1 &  Q2
         #  Clrn &  D2 & !Load & !Q2
         # !D2 & !Load &  Q2
         # !Clrn &  Q2;

-- Node name is 'Q3' = 'tmp3' 
-- Equation name is 'Q3', location is LC017, type is output.
 Q3      = DFFE( _EQ005 $  Clrn, GLOBAL( Clk),  VCC,  VCC,  VCC);
  _EQ005 =  Clrn &  Enp &  Ent &  Load &  Q0 &  Q1 &  Q2 &  Q3
         #  Clrn &  Enp &  Ent &  Load &  Q0 & !Q1 & !Q2 &  _X002
         #  Clrn &  Load & !Q3 &  _X003
         #  Clrn & !D3 & !Load;
  _X002  = EXP( Q0 &  Q1 &  Q2);
  _X003  = EXP( Enp &  Ent &  Q0 &  Q1 &  Q2);



--     Shareable expanders that are duplicated in multiple LABs:
--     (none)




Project Information  d:\source\aaaaaa\sourcecode\cpld\count_vhdl\count10_v.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Standard

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'MAX7000S' family

      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      PARALLEL_EXPANDERS                  = off
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SOFT_BUFFER_INSERTION               = on
      SUBFACTOR_EXTRACTION                = on
      TURBO_BIT                           = on
      XOR_SYNTHESIS                       = on
      IGNORE_SOFT_BUFFERS                 = off
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      One-Hot State Machine Encoding      = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:01
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:00
   Fitter                                 00:00:00
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:01
   --------------------------             --------
   Total Time                             00:00:02


Memory Allocated
-----------------

Peak memory allocated during compilation  = 3,817K