testapp_ps2_linker_script

source file application

/*******************************************************************/
/*                                                                 */
/* This file is automatically generated by linker script generator.*/
/*                                                                 */
/* Version: Xilinx EDK 7.1EDK_H.10.2                                  */
/*                                                                 */
/* Copyright (c) 2004 Xilinx, Inc.  All rights reserved.           */
/*                                                                 */
/* Description : PowerPC405 Linker Script                         */
/*                                                                 */
/*******************************************************************/

_STACK_SIZE = DEFINED(_STACK_SIZE) ? _STACK_SIZE : 0x400;
_HEAP_SIZE = DEFINED(_HEAP_SIZE) ? _HEAP_SIZE : 0x400;

/* Define Memories in the system */

MEMORY
{
   plb_bram_if_cntlr_1 : ORIGIN = 0xFFFF0000, LENGTH = 0x0000FFFF
}

/* Specify the default entry point to the program */

ENTRY(_boot)
STARTUP(boot.o)

/* Define the sections, and where they are mapped in memory */

SECTIONS
{
.vectors : {
   __vectors_start = .;
   *(.vectors)
   __vectors_end = .;
} > plb_bram_if_cntlr_1

.text : {
   __text_start = .;
   *(.text)
   *(.text.*)
   *(.gnu.linkonce.t*)
   __text_end = .;
} > plb_bram_if_cntlr_1

.rodata : {
   __rodata_start = .;
   *(.rodata)
   *(.rodata.*)
   *(.gnu.linkonce.r*)
   __rodata_end = .;
} > plb_bram_if_cntlr_1

.fixup : {
   __fixup_start = .;
   *(.fixup)
   __fixup_end = .;
} > plb_bram_if_cntlr_1

.got1 : {
   __got1_start = .;
   *(.got1)
   __got1_end = .;
} > plb_bram_if_cntlr_1

.got2 : {
   __got2_start = .;
   *(.got2)
   __got2_end = .;
} > plb_bram_if_cntlr_1

.sdata2 : {
   __sdata2_start = .;
   *(.sdata2)
   __sdata2_end = .;
} > plb_bram_if_cntlr_1

.sbss2 : {
   __sbss2_start = .;
   *(.sbss2)
   __sbss2_end = .;
} > plb_bram_if_cntlr_1

.data : {
   __data_start = .;
   *(.data)
   *(.data.*)
   *(.gnu.linkonce.d*)
   __data_end = .;
} > plb_bram_if_cntlr_1

.sdata : {
   __sdata_start = .;
   *(.sdata)
   __sdata_end = .;
} > plb_bram_if_cntlr_1

.sbss : {
   __sbss_start = .;
   *(.sbss)
   __sbss_end = .;
} > plb_bram_if_cntlr_1

.bss : {
   __bss_start = .;
   *(.bss)
   *(COMMON)
   . = ALIGN(4);
   __bss_end = .;
} > plb_bram_if_cntlr_1

.boot0 : {
   __boot0_start = .;
   *(.boot0)
   __boot0_end = .;
} > plb_bram_if_cntlr_1

.boot 0xFFFFFFFC : {
   __boot_start = .;
   *(.boot)
   __boot_end = .;
} 

.eh_frame : {
   __eh_frame_start = .;
   *(.eh_frame)
   __eh_frame_end = .;
} > plb_bram_if_cntlr_1

/* Generate Stack and Heap Sections */

bss_stack : {
   . += _STACK_SIZE;
   . = ALIGN(16);
   __stack = .;
} > plb_bram_if_cntlr_1

bss_heap : {
   . = ALIGN(16);
   _heap_start = .;
   . += _HEAP_SIZE;
   . = ALIGN(16);
   _heap_end = .;
} > plb_bram_if_cntlr_1

}