system.mhs

source file application

# 
# ##############################################################################
# 
# Created by Base System Builder Wizard for Xilinx EDK 7.1 Build EDK_H.10.2
# 
# Mon Mar 21 12:15:16 2005
# 
# Target Board:  Xilinx XUP Virtex-II Pro Development System Rev C
# Family:	 virtex2p
# Device:	 xc2vp30
# Package:	 ff896
# Speed Grade:	 -7
# 
# Processor: PPC 405
# Processor clock frequency: 100.000000 MHz
# Bus clock frequency: 100.000000 MHz
# Debug interface: FPGA JTAG
# On Chip Memory :  64 KB
# 
# ##############################################################################


 PARAMETER VERSION = 2.1.0


 PORT fpga_0_RS232_Uart_1_ctsN_pin = fpga_0_RS232_Uart_1_ctsN, DIR = INPUT
 PORT fpga_0_RS232_Uart_1_rtsN_pin = fpga_0_RS232_Uart_1_rtsN, DIR = OUTPUT
 PORT fpga_0_RS232_Uart_1_sin_pin = fpga_0_RS232_Uart_1_sin, DIR = INPUT
 PORT fpga_0_RS232_Uart_1_sout_pin = fpga_0_RS232_Uart_1_sout, DIR = OUTPUT
 PORT fpga_0_PS2_Ports_IO_ADAPTER_ps2_mouse_clk_pin = fpga_0_PS2_Ports_IO_ADAPTER_ps2_mouse_clk, DIR = INOUT
 PORT fpga_0_PS2_Ports_IO_ADAPTER_ps2_mouse_data_pin = fpga_0_PS2_Ports_IO_ADAPTER_ps2_mouse_data, DIR = INOUT
 PORT fpga_0_PS2_Ports_IO_ADAPTER_ps2_keyb_clk_pin = fpga_0_PS2_Ports_IO_ADAPTER_ps2_keyb_clk, DIR = INOUT
 PORT fpga_0_PS2_Ports_IO_ADAPTER_ps2_keyb_data_pin = fpga_0_PS2_Ports_IO_ADAPTER_ps2_keyb_data, DIR = INOUT
 PORT sys_clk_pin = dcm_clk_s, DIR = INPUT
 PORT sys_rst_pin = sys_rst_s, DIR = INPUT


BEGIN ppc405
 PARAMETER INSTANCE = ppc405_0
 PARAMETER HW_VER = 2.00.c
 BUS_INTERFACE JTAGPPC = jtagppc_0_0
 BUS_INTERFACE IPLB = plb
 BUS_INTERFACE DPLB = plb
 PORT PLBCLK = sys_clk_s
 PORT C405RSTCHIPRESETREQ = C405RSTCHIPRESETREQ
 PORT C405RSTCORERESETREQ = C405RSTCORERESETREQ
 PORT C405RSTSYSRESETREQ = C405RSTSYSRESETREQ
 PORT RSTC405RESETCHIP = RSTC405RESETCHIP
 PORT RSTC405RESETCORE = RSTC405RESETCORE
 PORT RSTC405RESETSYS = RSTC405RESETSYS
 PORT EICC405EXTINPUTIRQ = EICC405EXTINPUTIRQ
 PORT CPMC405CLOCK = sys_clk_s
END

BEGIN ppc405
 PARAMETER INSTANCE = ppc405_1
 PARAMETER HW_VER = 2.00.c
 BUS_INTERFACE JTAGPPC = jtagppc_0_1
END

BEGIN jtagppc_cntlr
 PARAMETER INSTANCE = jtagppc_0
 PARAMETER HW_VER = 2.00.a
 BUS_INTERFACE JTAGPPC0 = jtagppc_0_0
 BUS_INTERFACE JTAGPPC1 = jtagppc_0_1
END

BEGIN proc_sys_reset
 PARAMETER INSTANCE = reset_block
 PARAMETER HW_VER = 1.00.a
 PARAMETER C_EXT_RESET_HIGH = 0
 PORT Ext_Reset_In = sys_rst_s
 PORT Slowest_sync_clk = sys_clk_s
 PORT Chip_Reset_Req = C405RSTCHIPRESETREQ
 PORT Core_Reset_Req = C405RSTCORERESETREQ
 PORT System_Reset_Req = C405RSTSYSRESETREQ
 PORT Rstc405resetchip = RSTC405RESETCHIP
 PORT Rstc405resetcore = RSTC405RESETCORE
 PORT Rstc405resetsys = RSTC405RESETSYS
 PORT Bus_Struct_Reset = sys_bus_reset
 PORT Dcm_locked = dcm_0_lock
END

BEGIN plb_v34
 PARAMETER INSTANCE = plb
 PARAMETER HW_VER = 1.02.a
 PARAMETER C_DCR_INTFCE = 0
 PARAMETER C_EXT_RESET_HIGH = 1
 PORT SYS_Rst = sys_bus_reset
 PORT PLB_Clk = sys_clk_s
END

BEGIN opb_v20
 PARAMETER INSTANCE = opb
 PARAMETER HW_VER = 1.10.c
 PARAMETER C_EXT_RESET_HIGH = 1
 PORT SYS_Rst = sys_bus_reset
 PORT OPB_Clk = sys_clk_s
END

BEGIN plb2opb_bridge
 PARAMETER INSTANCE = plb2opb
 PARAMETER HW_VER = 1.01.a
 PARAMETER C_DCR_INTFCE = 0
 PARAMETER C_NUM_ADDR_RNG = 1
 PARAMETER C_RNG0_BASEADDR = 0x00000000
 PARAMETER C_RNG0_HIGHADDR = 0x7fffffff
 BUS_INTERFACE SPLB = plb
 BUS_INTERFACE MOPB = opb
 PORT PLB_Clk = sys_clk_s
 PORT OPB_Clk = sys_clk_s
END

BEGIN opb_uart16550
 PARAMETER INSTANCE = RS232_Uart_1
 PARAMETER HW_VER = 1.00.c
 PARAMETER C_IS_A_16550 = 1
 PARAMETER C_BASEADDR = 0x40400000
 PARAMETER C_HIGHADDR = 0x4040ffff
 BUS_INTERFACE SOPB = opb
 PORT OPB_Clk = sys_clk_s
 PORT IP2INTC_Irpt = RS232_Uart_1_IP2INTC_Irpt
 PORT ctsN = fpga_0_RS232_Uart_1_ctsN
 PORT rtsN = fpga_0_RS232_Uart_1_rtsN
 PORT sin = fpga_0_RS232_Uart_1_sin
 PORT sout = fpga_0_RS232_Uart_1_sout
END

BEGIN opb_ps2_dual_ref
 PARAMETER INSTANCE = PS2_Ports
 PARAMETER HW_VER = 1.00.a
 PARAMETER C_BASEADDR = 0x7a400000
 PARAMETER C_HIGHADDR = 0x7a40ffff
 BUS_INTERFACE SOPB = opb
 PORT OPB_Clk = sys_clk_s
 PORT Clkin1 = PS2_Ports_Clkin1_PS2_Ports_IO_ADAPTER_ps2_clk_rx_1
 PORT Clkpd1 = PS2_Ports_Clkpd1_PS2_Ports_IO_ADAPTER_ps2_clk_tx_1
 PORT Rx1 = PS2_Ports_IO_ADAPTER_ps2_d_rx_1_PS2_Ports_Rx1
 PORT Txpd1 = PS2_Ports_IO_ADAPTER_ps2_d_tx_1_PS2_Ports_Txpd1
 PORT Clkin2 = PS2_Ports_Clkin2_PS2_Ports_IO_ADAPTER_ps2_clk_rx_2
 PORT Clkpd2 = PS2_Ports_Clkpd2_PS2_Ports_IO_ADAPTER_ps2_clk_tx_2
 PORT Rx2 = PS2_Ports_IO_ADAPTER_ps2_d_rx_2_PS2_Ports_Rx2
 PORT Txpd2 = PS2_Ports_IO_ADAPTER_ps2_d_tx_2_PS2_Ports_Txpd2
END

BEGIN plb_bram_if_cntlr
 PARAMETER INSTANCE = plb_bram_if_cntlr_1
 PARAMETER HW_VER = 1.00.b
 PARAMETER c_plb_clk_period_ps = 10000
 PARAMETER c_baseaddr = 0xffff0000
 PARAMETER c_highaddr = 0xffffffff
 BUS_INTERFACE SPLB = plb
 BUS_INTERFACE PORTA = plb_bram_if_cntlr_1_port
 PORT PLB_Clk = sys_clk_s
END

BEGIN bram_block
 PARAMETER INSTANCE = plb_bram_if_cntlr_1_bram
 PARAMETER HW_VER = 1.00.a
 BUS_INTERFACE PORTA = plb_bram_if_cntlr_1_port
END

BEGIN opb_intc
 PARAMETER INSTANCE = opb_intc_0
 PARAMETER HW_VER = 1.00.c
 PARAMETER C_BASEADDR = 0x41200000
 PARAMETER C_HIGHADDR = 0x4120ffff
 BUS_INTERFACE SOPB = opb
 PORT Irq = EICC405EXTINPUTIRQ
 PORT Intr = RS232_Uart_1_IP2INTC_Irpt
END

BEGIN dual_ps2_ioadapter
 PARAMETER INSTANCE = PS2_Ports_IO_ADAPTER
 PARAMETER HW_VER = 1.00.a
 PORT ps2_clk_rx_1 = PS2_Ports_Clkin1_PS2_Ports_IO_ADAPTER_ps2_clk_rx_1
 PORT ps2_clk_tx_1 = PS2_Ports_Clkpd1_PS2_Ports_IO_ADAPTER_ps2_clk_tx_1
 PORT ps2_d_rx_1 = PS2_Ports_IO_ADAPTER_ps2_d_rx_1_PS2_Ports_Rx1
 PORT ps2_d_tx_1 = PS2_Ports_IO_ADAPTER_ps2_d_tx_1_PS2_Ports_Txpd1
 PORT ps2_clk_rx_2 = PS2_Ports_Clkin2_PS2_Ports_IO_ADAPTER_ps2_clk_rx_2
 PORT ps2_clk_tx_2 = PS2_Ports_Clkpd2_PS2_Ports_IO_ADAPTER_ps2_clk_tx_2
 PORT ps2_d_rx_2 = PS2_Ports_IO_ADAPTER_ps2_d_rx_2_PS2_Ports_Rx2
 PORT ps2_d_tx_2 = PS2_Ports_IO_ADAPTER_ps2_d_tx_2_PS2_Ports_Txpd2
 PORT ps2_mouse_clk = fpga_0_PS2_Ports_IO_ADAPTER_ps2_mouse_clk
 PORT ps2_mouse_data = fpga_0_PS2_Ports_IO_ADAPTER_ps2_mouse_data
 PORT ps2_keyb_clk = fpga_0_PS2_Ports_IO_ADAPTER_ps2_keyb_clk
 PORT ps2_keyb_data = fpga_0_PS2_Ports_IO_ADAPTER_ps2_keyb_data
END

BEGIN dcm_module
 PARAMETER INSTANCE = dcm_0
 PARAMETER HW_VER = 1.00.a
 PARAMETER C_CLK0_BUF = TRUE
 PARAMETER C_CLKIN_PERIOD = 10.000000
 PARAMETER C_CLK_FEEDBACK = 1X
 PARAMETER C_EXT_RESET_HIGH = 1
 PORT CLKIN = dcm_clk_s
 PORT CLK0 = sys_clk_s
 PORT CLKFB = sys_clk_s
 PORT RST = net_gnd
 PORT LOCKED = dcm_0_lock
END