recorder.vhd

audio file on virtex

-------------------------------------------------------------------------------
-- recorder.vhd
--
-- Author(s):     Jorgen Peddersen
-- Created:       Dec 2000
-- Last Modified: Dec 2000
-- 
-- Records about 10 seconds of stereo input from the stereo decoder into RAM.
-- when start is asserted, the recorder will keep recording until stop is
-- asserted or the end of RAM is reached.  If the end of RAM is reached, then
-- the output full is asserted.
-------------------------------------------------------------------------------

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;

entity recorder is
    port (
        start: in STD_LOGIC;							-- assert to start recording
        stop: in STD_LOGIC;								-- assert to stop recording
        rstn: in STD_LOGIC;								-- asynchronous active low reset
        sclk: in STD_LOGIC;								-- sampling clock signal
        lrck: in STD_LOGIC;								-- left/right select clock
        sdin: in STD_LOGIC;								-- serial data in from chip
        dataOut: out STD_LOGIC_VECTOR (31 downto 0);	-- data to RAM
        address: out STD_LOGIC_VECTOR (18 downto 0);	-- address of RAM
        full: out STD_LOGIC;							-- indicates when RAM is full
        write: out STD_LOGIC							-- write signal to RAM
    );
end recorder;

architecture recorder_arch of recorder is

-- State signals
type STATETYPE is (stReset, stWait, stIdleL, stDataL, stIdleR, stDataR, stStop);
signal presState : STATETYPE;
signal nextState : STATETYPE;

signal addressInt : STD_LOGIC_VECTOR (18 downto 0);		-- internal address value
signal dataInt : STD_LOGIC_VECTOR (31 downto 0);		-- internal data value
signal incAddress : STD_LOGIC;							-- increment address
signal clrAddress : STD_LOGIC;							-- reset address to 0

signal shiftin : STD_LOGIC;								-- shift serial data into dataInt

signal dataCounter : STD_LOGIC_VECTOR (3 downto 0);		-- count how many shifts have occured
signal incData : STD_LOGIC;								-- increment data counter

begin

	process(sclk, rstn)
	begin
		if rstn = '0' then
			presState <= stReset;
			addressInt <= (others => '0');
			dataInt <= (others => '0');
			dataCounter <= (others => '0');
		elsif sclk'event and sclk = '1' then
			presState <= nextState;			-- go to next state
			
			-- handle RAM address and its signals
			if clrAddress = '1' then
				addressInt <= (others => '0');
			elsif incAddress = '1' then
				addressInt <= addressInt + 1;
			end if;
			
			-- shift in serial data MSB first
			if shiftIn = '1' then
				dataInt <= dataInt(30 downto 0) & sdin;
			end if;
			
			-- handle dataCounter, it automatically overflows at 16
			if incData = '1' then
				dataCounter <= dataCounter + 1;
			end if;
			
		end if;
	end process;
	
	process(presState, LRCK, dataCounter, addressInt, start, stop)
	begin
		-- default values of signals
		shiftin <= '0';
		clrAddress <= '0';
		incAddress <= '0';
		incData <= '0';
		write <= '0';
		full <= '0';
				
		case presState is
			when stReset =>
				-- wait for start button to be pushed
				if start = '0' then
					nextState <= stReset;
				else
					nextState <= stWait;
				end if;
			when stWait =>
				-- wait for right channel to be active
				if LRCK = '1' then
					nextState <= stWait;
				else
					nextState <= stIdleL;
					clrAddress <= '1';		-- reset address
				end if;
			when stIdleL =>
				-- start recording when left channel becomes active
				if LRCK = '0' then
					nextState <= stIdleL;
				else
					nextState <= stDataL;
					-- get first bit of data
					shiftIn <= '1';
					incData <= '1';
				end if;
			when stDataL =>
				-- load data until 16 bits are received.
				if dataCounter /= 0 then
					-- get data until counter overflows
					nextState <= stDataL;
					shiftIn <= '1';
					incData <= '1';
				else
					-- wait for right channel data
					nextState <= stIdleR;
				end if;
			when stIdleR =>
				-- start recording when right channel becomes active				
				if LRCK = '1' then
					nextState <= stIdleR;
				else
					-- get first bit of data
					nextState <= stDataR;
					shiftIn <= '1';
					incData <= '1';
				end if;					
			when stDataR =>
				-- load data until 16 bits are received.
				if dataCounter /= 0 then
					-- get data until counter overflows
					nextState <= stDataR;
					shiftIn <= '1';
					incData <= '1';
				else
					-- Write data to RAM and go to next address
					nextState <= stStop;
					write <= '1';
					incAddress <= '1';
				end if;
			when stStop =>
				-- Check if recording should finish
				if addressInt = 0 then
					-- address has overflowed so don't write any more data until start is asserted
					if start = '1' then
						nextState <= stWait;
					else
						nextState <= stStop;
						full <= '1';
					end if;
				elsif stop = '1' then
					-- if the stop signal is asserted then wait for the start signal 
					nextState <= stReset;
				else
					-- There is more RAM left so keep recording
					nextState <= stIdleL;
				end if;
		end case;		
	end process;
	
	-- map internal signals to outputs
	dataOut <= dataInt;
	address <= addressInt;				

end recorder_arch;