sq.vhd

vhdl源代码,可以开16比特的平方根

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity sq is
	port(M:in std_logic_vector(7 downto 0);
		  clk,ret:in bit;
	  	  N:out std_logic_vector(3 downto 0)
	     );
end;

architecture kg of sq is
   signal min : std_logic_vector(7 downto 0);
	signal rsu1 : std_logic_vector(3 downto 0);
	signal rsu2 : std_logic_vector(3 downto 0);
	signal tmp : std_logic_vector(7 downto 0);
	--signal tmp1 : std_logic_vector(7 downto 0);
	signal ttp : std_logic_vector(7 downto 0); 
	signal clc : std_logic_vector(3 downto 0);  
	signal cul : bit;
begin
    process (clk)
    begin
        if (ret = '1' or M = "00000000")then
            rsu2 <= "0000";
            rsu1 <= "0000";
            tmp <= "00000000";
            ttp <= "00000000";
            clc <= "0000";
            Min <= M;
            --tmp1 <= M;
        elsif (clk'event and clk = '1') then
                if (cul = '1')then
                    if (tmp >= ttp )then
                       tmp <= tmp - ttp;
                       rsu1 <= rsu1 + '1';
                    end if;
                    cul <= '0';
                 
                elsif (clc /= "0100")then
                 
                    tmp(7 downto 2) <= tmp (5 downto 0);
                    tmp(1 downto 0) <= Min(7 downto 6);
                    Min (7 downto 2) <= Min (5 downto 0);
                    Min (1 downto 0 ) <= "00";
                    rsu1 (3 downto 1) <= rsu1 (2 downto 0);
                    rsu1(0) <= '0';
                    ttp(7 downto 6) <= ttp (5 downto 4);
                    ttp (5 downto 2)<= rsu1 (3 downto 0);
                    ttp(1 downto 0) <= "01";
        
                    cul <= '1';

                    clc <= clc + 1;
                 
              elsif (clc = "0100" and cul = '0') then
 
                   rsu2 <= rsu1;
                   --cul <= '0';
              end if;
            --end if;

        end if; 
        N <= rsu2;   
    end process;
end kg;