sq_tb.vhd

vhdl源代码,可以开16比特的平方根

library IEEE;
use IEEE.std_logic_1164.all;

entity TB_SQ is
end TB_SQ;

architecture BEH of TB_SQ is

-- Input data
  constant A_CON : std_logic_vector ( 7 downto 0 ) := ("10010000");
  
  -- define clock period
  constant PERIOD : time := 10 ns;

   signal W_M        : std_logic_vector ( 7 downto 0 ):= ( "10010000");
   signal W_CLK      : bit;
   signal W_RET      : bit := '1'; 
   signal W_N        : std_logic_vector ( 3 downto 0 );

   component SQ
      port(M        : in std_logic_vector ( 7 downto 0 );
           CLK      : in bit ;
           RET      : in bit ;
           N        : out std_logic_vector ( 3 downto 0 ) );

   end component;

begin

   DUT : SQ
      port map(M        => W_M,
               CLK      => W_CLK,
               RET      => W_RET,
               --ENABLE   => W_ENABLE,
               N        => W_N);

   W_CLK <= not W_CLK after PERIOD/2;


   STIMULI : process
   begin
      W_M        <= A_CON;
      W_RET      <= '0' after 35 ns;

      wait for PERIOD;
      --wait;
   end process STIMULI;

end BEH;