send_test.map.rpt

串口通讯

; HDL message level                                                              ; Level2             ; Level2             ;
; Suppress Register Optimization Related Messages                                ; Off                ; Off                ;
; Number of Removed Registers Reported in Synthesis Report                       ; 100                ; 100                ;
; Clock MUX Protection                                                           ; On                 ; On                 ;
; Block Design Naming                                                            ; Auto               ; Auto               ;
+--------------------------------------------------------------------------------+--------------------+--------------------+


+----------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read                                                                                           ;
+----------------------------------+-----------------+------------------------+----------------------------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Type              ; File Name with Absolute Path                       ;
+----------------------------------+-----------------+------------------------+----------------------------------------------------+
; send_test.v                      ; yes             ; User Verilog HDL File  ; G:/我的文档/uart/altera_uart/send_test/send_test.v ;
+----------------------------------+-----------------+------------------------+----------------------------------------------------+


+-----------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary         ;
+---------------------------------------------+-------+
; Resource                                    ; Usage ;
+---------------------------------------------+-------+
; Estimated Total logic elements              ; 28    ;
;                                             ;       ;
; Total combinational functions               ; 28    ;
; Logic element usage by number of LUT inputs ;       ;
;     -- 4 input functions                    ; 8     ;
;     -- 3 input functions                    ; 4     ;
;     -- <=2 input functions                  ; 16    ;
;                                             ;       ;
; Logic elements by mode                      ;       ;
;     -- normal mode                          ; 13    ;
;     -- arithmetic mode                      ; 15    ;
;                                             ;       ;
; Total registers                             ; 22    ;
;     -- Dedicated logic registers            ; 22    ;
;     -- I/O registers                        ; 0     ;
;                                             ;       ;
; I/O pins                                    ; 12    ;
; Maximum fan-out node                        ; clk   ;
; Maximum fan-out                             ; 22    ;
; Total fan-out                               ; 136   ;
; Average fan-out                             ; 2.19  ;
+---------------------------------------------+-------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                         ;
+----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+---------------------+--------------+
; Compilation Hierarchy Node ; LC Combinationals ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name ; Library Name ;
+----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+---------------------+--------------+
; |send_test                 ; 28 (28)           ; 22 (22)      ; 0           ; 0            ; 0       ; 0         ; 12   ; 0            ; |send_test          ; work         ;
+----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+---------------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 22    ;
; Number of registers using Synchronous Clear  ; 0     ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 0     ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 16    ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+---------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: Top-level Entity: |send_test ;
+-----------------------+----------+----------------------------------------+
; Parameter Name        ; Value    ; Type                                   ;
+-----------------------+----------+----------------------------------------+
; ClkFrequency          ; 50000000 ; Signed Integer                         ;
; Baud                  ; 9600     ; Signed Integer                         ;
; RegisterInputData     ; 1        ; Signed Integer                         ;
; BaudGeneratorAccWidth ; 16       ; Signed Integer                         ;
+-----------------------+----------+----------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 7.2 Build 207 03/18/2008 Service Pack 3 SJ Full Version
    Info: Processing started: Mon Aug 11 16:58:36 2008
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off send_test -c send_test
Info: Found 1 design units, including 1 entities, in source file send_test.v
    Info: Found entity 1: send_test
Info: Elaborating entity "send_test" for the top level hierarchy
Warning (10036): Verilog HDL or VHDL warning at send_test.v(80): object "TxD_dataD" assigned a value but never read
Warning (10230): Verilog HDL assignment warning at send_test.v(63): truncated value with size 32 to match size of target (17)
Warning: Design contains 8 input pin(s) that do not drive logic
    Warning (15610): No output dependent on input pin "TxD_data[0]"
    Warning (15610): No output dependent on input pin "TxD_data[1]"
    Warning (15610): No output dependent on input pin "TxD_data[2]"
    Warning (15610): No output dependent on input pin "TxD_data[3]"
    Warning (15610): No output dependent on input pin "TxD_data[4]"
    Warning (15610): No output dependent on input pin "TxD_data[5]"
    Warning (15610): No output dependent on input pin "TxD_data[6]"
    Warning (15610): No output dependent on input pin "TxD_data[7]"
Info: Implemented 40 device resources after synthesis - the final resource count might be different
    Info: Implemented 10 input pins
    Info: Implemented 2 output pins
    Info: Implemented 28 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 11 warnings
    Info: Allocated 144 megabytes of memory during processing
    Info: Processing ended: Mon Aug 11 16:58:37 2008
    Info: Elapsed time: 00:00:01