📄 send_test.tan.rpt
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+---------------------------------------------------------------------+
; tsu ;
+-------+--------------+------------+-----------+----------+----------+
; Slack ; Required tsu ; Actual tsu ; From ; To ; To Clock ;
+-------+--------------+------------+-----------+----------+----------+
; N/A ; None ; 4.751 ns ; TxD_start ; state[0] ; clk ;
+-------+--------------+------------+-----------+----------+----------+
+----------------------------------------------------------------------+
; tco ;
+-------+--------------+------------+----------+----------+------------+
; Slack ; Required tco ; Actual tco ; From ; To ; From Clock ;
+-------+--------------+------------+----------+----------+------------+
; N/A ; None ; 8.583 ns ; TxD~reg0 ; TxD ; clk ;
; N/A ; None ; 8.120 ns ; state[0] ; TxD_busy ; clk ;
; N/A ; None ; 8.057 ns ; state[3] ; TxD_busy ; clk ;
; N/A ; None ; 7.732 ns ; state[2] ; TxD_busy ; clk ;
; N/A ; None ; 7.647 ns ; state[1] ; TxD_busy ; clk ;
+-------+--------------+------------+----------+----------+------------+
+---------------------------------------------------------------------------+
; th ;
+---------------+-------------+-----------+-----------+----------+----------+
; Minimum Slack ; Required th ; Actual th ; From ; To ; To Clock ;
+---------------+-------------+-----------+-----------+----------+----------+
; N/A ; None ; -4.485 ns ; TxD_start ; state[0] ; clk ;
+---------------+-------------+-----------+-----------+----------+----------+
+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
Info: Version 7.2 Build 207 03/18/2008 Service Pack 3 SJ Full Version
Info: Processing started: Mon Aug 11 16:58:46 2008
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off send_test -c send_test --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
Info: Assuming node "clk" is an undefined clock
Info: Clock "clk" has Internal fmax of 287.69 MHz between source register "BaudGeneratorAcc[0]" and destination register "BaudGeneratorAcc[16]" (period= 3.476 ns)
Info: + Longest register to register delay is 3.212 ns
Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X1_Y2_N15; Fanout = 3; REG Node = 'BaudGeneratorAcc[0]'
Info: 2: + IC(0.669 ns) + CELL(0.621 ns) = 1.290 ns; Loc. = LCCOMB_X2_Y2_N0; Fanout = 2; COMB Node = 'BaudGeneratorAcc[1]~482'
Info: 3: + IC(0.000 ns) + CELL(0.086 ns) = 1.376 ns; Loc. = LCCOMB_X2_Y2_N2; Fanout = 2; COMB Node = 'BaudGeneratorAcc[2]~484'
Info: 4: + IC(0.000 ns) + CELL(0.086 ns) = 1.462 ns; Loc. = LCCOMB_X2_Y2_N4; Fanout = 2; COMB Node = 'BaudGeneratorAcc[3]~486'
Info: 5: + IC(0.000 ns) + CELL(0.086 ns) = 1.548 ns; Loc. = LCCOMB_X2_Y2_N6; Fanout = 2; COMB Node = 'BaudGeneratorAcc[4]~488'
Info: 6: + IC(0.000 ns) + CELL(0.086 ns) = 1.634 ns; Loc. = LCCOMB_X2_Y2_N8; Fanout = 2; COMB Node = 'BaudGeneratorAcc[5]~490'
Info: 7: + IC(0.000 ns) + CELL(0.086 ns) = 1.720 ns; Loc. = LCCOMB_X2_Y2_N10; Fanout = 2; COMB Node = 'BaudGeneratorAcc[6]~492'
Info: 8: + IC(0.000 ns) + CELL(0.086 ns) = 1.806 ns; Loc. = LCCOMB_X2_Y2_N12; Fanout = 2; COMB Node = 'BaudGeneratorAcc[7]~494'
Info: 9: + IC(0.000 ns) + CELL(0.190 ns) = 1.996 ns; Loc. = LCCOMB_X2_Y2_N14; Fanout = 2; COMB Node = 'BaudGeneratorAcc[8]~496'
Info: 10: + IC(0.000 ns) + CELL(0.086 ns) = 2.082 ns; Loc. = LCCOMB_X2_Y2_N16; Fanout = 2; COMB Node = 'BaudGeneratorAcc[9]~498'
Info: 11: + IC(0.000 ns) + CELL(0.086 ns) = 2.168 ns; Loc. = LCCOMB_X2_Y2_N18; Fanout = 2; COMB Node = 'BaudGeneratorAcc[10]~500'
Info: 12: + IC(0.000 ns) + CELL(0.086 ns) = 2.254 ns; Loc. = LCCOMB_X2_Y2_N20; Fanout = 2; COMB Node = 'BaudGeneratorAcc[11]~502'
Info: 13: + IC(0.000 ns) + CELL(0.086 ns) = 2.340 ns; Loc. = LCCOMB_X2_Y2_N22; Fanout = 2; COMB Node = 'BaudGeneratorAcc[12]~504'
Info: 14: + IC(0.000 ns) + CELL(0.086 ns) = 2.426 ns; Loc. = LCCOMB_X2_Y2_N24; Fanout = 2; COMB Node = 'BaudGeneratorAcc[13]~506'
Info: 15: + IC(0.000 ns) + CELL(0.086 ns) = 2.512 ns; Loc. = LCCOMB_X2_Y2_N26; Fanout = 2; COMB Node = 'BaudGeneratorAcc[14]~508'
Info: 16: + IC(0.000 ns) + CELL(0.086 ns) = 2.598 ns; Loc. = LCCOMB_X2_Y2_N28; Fanout = 1; COMB Node = 'BaudGeneratorAcc[15]~510'
Info: 17: + IC(0.000 ns) + CELL(0.506 ns) = 3.104 ns; Loc. = LCCOMB_X2_Y2_N30; Fanout = 1; COMB Node = 'BaudGeneratorAcc[16]~511'
Info: 18: + IC(0.000 ns) + CELL(0.108 ns) = 3.212 ns; Loc. = LCFF_X2_Y2_N31; Fanout = 5; REG Node = 'BaudGeneratorAcc[16]'
Info: Total cell delay = 2.543 ns ( 79.17 % )
Info: Total interconnect delay = 0.669 ns ( 20.83 % )
Info: - Smallest clock skew is 0.000 ns
Info: + Shortest clock path from clock "clk" to destination register is 2.742 ns
Info: 1: + IC(0.000 ns) + CELL(1.100 ns) = 1.100 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'
Info: 2: + IC(0.143 ns) + CELL(0.000 ns) = 1.243 ns; Loc. = CLKCTRL_G2; Fanout = 22; COMB Node = 'clk~clkctrl'
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