receive_test.map.rpt

串口通讯

+-----------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read                                                                                            ;
+----------------------------------+-----------------+------------------------+-----------------------------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Type              ; File Name with Absolute Path                        ;
+----------------------------------+-----------------+------------------------+-----------------------------------------------------+
; receive_test.v                   ; yes             ; User Verilog HDL File  ; G:/我的文档/uart/altera_uart/receive/receive_test.v ;
+----------------------------------+-----------------+------------------------+-----------------------------------------------------+


+-----------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary         ;
+---------------------------------------------+-------+
; Resource                                    ; Usage ;
+---------------------------------------------+-------+
; Estimated Total logic elements              ; 47    ;
;                                             ;       ;
; Total combinational functions               ; 47    ;
; Logic element usage by number of LUT inputs ;       ;
;     -- 4 input functions                    ; 15    ;
;     -- 3 input functions                    ; 6     ;
;     -- <=2 input functions                  ; 26    ;
;                                             ;       ;
; Logic elements by mode                      ;       ;
;     -- normal mode                          ; 30    ;
;     -- arithmetic mode                      ; 17    ;
;                                             ;       ;
; Total registers                             ; 43    ;
;     -- Dedicated logic registers            ; 43    ;
;     -- I/O registers                        ; 0     ;
;                                             ;       ;
; I/O pins                                    ; 14    ;
; Maximum fan-out node                        ; clk   ;
; Maximum fan-out                             ; 43    ;
; Total fan-out                               ; 245   ;
; Average fan-out                             ; 2.36  ;
+---------------------------------------------+-------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                         ;
+----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+---------------------+--------------+
; Compilation Hierarchy Node ; LC Combinationals ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name ; Library Name ;
+----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+---------------------+--------------+
; |receive_test              ; 47 (47)           ; 43 (43)      ; 0           ; 0            ; 0       ; 0         ; 14   ; 0            ; |receive_test       ; work         ;
+----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+---------------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+--------------------------------------------------------------------------------+
; Registers Removed During Synthesis                                             ;
+---------------------------------------+----------------------------------------+
; Register name                         ; Reason for Removal                     ;
+---------------------------------------+----------------------------------------+
; Baud8GeneratorAcc[1..2]               ; Merged with Baud8GeneratorAcc[0]       ;
; Baud8GeneratorAcc[0]                  ; Stuck at GND due to stuck port data_in ;
; Total Number of Removed Registers = 3 ;                                        ;
+---------------------------------------+----------------------------------------+


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 43    ;
; Number of registers using Synchronous Clear  ; 5     ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 0     ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 18    ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+--------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (Restructuring Performed)                                                                             ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+------------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output   ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+------------------------------+
; 3:1                ; 3 bits    ; 6 LEs         ; 3 LEs                ; 3 LEs                  ; Yes        ; |receive_test|bit_spacing[0] ;
; 3:1                ; 2 bits    ; 4 LEs         ; 0 LEs                ; 4 LEs                  ; Yes        ; |receive_test|RxD_cnt_inv[0] ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+------------------------------+


+------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: Top-level Entity: |receive_test ;
+------------------------+----------+------------------------------------------+
; Parameter Name         ; Value    ; Type                                     ;
+------------------------+----------+------------------------------------------+
; ClkFrequency           ; 50000000 ; Signed Integer                           ;
; Baud                   ; 115200   ; Signed Integer                           ;
; Baud8                  ; 921600   ; Signed Integer                           ;
; Baud8GeneratorAccWidth ; 16       ; Signed Integer                           ;
+------------------------+----------+------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 7.2 Build 207 03/18/2008 Service Pack 3 SJ Full Version
    Info: Processing started: Mon Aug 11 17:01:34 2008
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off receive_test -c receive_test
Info: Found 1 design units, including 1 entities, in source file receive_test.v
    Info: Found entity 1: receive_test
Info: Elaborating entity "receive_test" for the top level hierarchy
Warning (10036): Verilog HDL or VHDL warning at receive_test.v(114): object "RxD_data_error" assigned a value but never read
Warning (10230): Verilog HDL assignment warning at receive_test.v(25): truncated value with size 32 to match size of target (17)
Info: Duplicate registers merged to single register
    Info: Duplicate register "Baud8GeneratorAcc[1]" merged to single register "Baud8GeneratorAcc[0]"
    Info: Duplicate register "Baud8GeneratorAcc[2]" merged to single register "Baud8GeneratorAcc[0]"
Warning (14130): Reduced register "Baud8GeneratorAcc[0]" with stuck data_in port to stuck value GND
Info: Implemented 69 device resources after synthesis - the final resource count might be different
    Info: Implemented 2 input pins
    Info: Implemented 12 output pins
    Info: Implemented 55 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 3 warnings
    Info: Allocated 143 megabytes of memory during processing
    Info: Processing ended: Mon Aug 11 17:01:36 2008
    Info: Elapsed time: 00:00:02