receive_test.tan.rpt

串口通讯

+-----------------------------------------------------------------------+
; tsu                                                                   ;
+-------+--------------+------------+------+-----------------+----------+
; Slack ; Required tsu ; Actual tsu ; From ; To              ; To Clock ;
+-------+--------------+------------+------+-----------------+----------+
; N/A   ; None         ; 5.426 ns   ; RxD  ; RxD_sync_inv[0] ; clk      ;
+-------+--------------+------------+------+-----------------+----------+


+-----------------------------------------------------------------------------------------+
; tco                                                                                     ;
+-------+--------------+------------+----------------------+-----------------+------------+
; Slack ; Required tco ; Actual tco ; From                 ; To              ; From Clock ;
+-------+--------------+------------+----------------------+-----------------+------------+
; N/A   ; None         ; 10.415 ns  ; RxD_data[3]~reg0     ; RxD_data[3]     ; clk        ;
; N/A   ; None         ; 10.383 ns  ; RxD_data[4]~reg0     ; RxD_data[4]     ; clk        ;
; N/A   ; None         ; 9.462 ns   ; RxD_data[2]~reg0     ; RxD_data[2]     ; clk        ;
; N/A   ; None         ; 9.033 ns   ; RxD_data[0]~reg0     ; RxD_data[0]     ; clk        ;
; N/A   ; None         ; 8.937 ns   ; gap_count[4]         ; RxD_idle        ; clk        ;
; N/A   ; None         ; 8.589 ns   ; RxD_data[1]~reg0     ; RxD_data[1]     ; clk        ;
; N/A   ; None         ; 8.513 ns   ; RxD_data[5]~reg0     ; RxD_data[5]     ; clk        ;
; N/A   ; None         ; 7.943 ns   ; RxD_endofpacket~reg0 ; RxD_endofpacket ; clk        ;
; N/A   ; None         ; 7.919 ns   ; RxD_data[7]~reg0     ; RxD_data[7]     ; clk        ;
; N/A   ; None         ; 7.639 ns   ; RxD_data_ready~reg0  ; RxD_data_ready  ; clk        ;
; N/A   ; None         ; 7.220 ns   ; RxD_data[6]~reg0     ; RxD_data[6]     ; clk        ;
; N/A   ; None         ; 7.196 ns   ; out_clk~reg0         ; out_clk         ; clk        ;
+-------+--------------+------------+----------------------+-----------------+------------+


+-----------------------------------------------------------------------------+
; th                                                                          ;
+---------------+-------------+-----------+------+-----------------+----------+
; Minimum Slack ; Required th ; Actual th ; From ; To              ; To Clock ;
+---------------+-------------+-----------+------+-----------------+----------+
; N/A           ; None        ; -5.160 ns ; RxD  ; RxD_sync_inv[0] ; clk      ;
+---------------+-------------+-----------+------+-----------------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
    Info: Version 7.2 Build 207 03/18/2008 Service Pack 3 SJ Full Version
    Info: Processing started: Mon Aug 11 17:01:45 2008
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off receive_test -c receive_test --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk" is an undefined clock
Info: Clock "clk" has Internal fmax of 246.67 MHz between source register "bit_spacing[3]" and destination register "RxD_data[0]~reg0" (period= 4.054 ns)
    Info: + Longest register to register delay is 3.787 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X9_Y1_N5; Fanout = 2; REG Node = 'bit_spacing[3]'
        Info: 2: + IC(0.440 ns) + CELL(0.571 ns) = 1.011 ns; Loc. = LCCOMB_X9_Y1_N8; Fanout = 7; COMB Node = 'Equal2~40'
        Info: 3: + IC(0.378 ns) + CELL(0.589 ns) = 1.978 ns; Loc. = LCCOMB_X9_Y1_N10; Fanout = 8; COMB Node = 'always5~12'
        Info: 4: + IC(0.954 ns) + CELL(0.855 ns) = 3.787 ns; Loc. = LCFF_X7_Y1_N17; Fanout = 1; REG Node = 'RxD_data[0]~reg0'
        Info: Total cell delay = 2.015 ns ( 53.21 % )
        Info: Total interconnect delay = 1.772 ns ( 46.79 % )
    Info: - Smallest clock skew is -0.003 ns
        Info: + Shortest clock path from clock "clk" to destination register is 2.751 ns
            Info: 1: + IC(0.000 ns) + CELL(1.100 ns) = 1.100 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'
            Info: 2: + IC(0.143 ns) + CELL(0.000 ns) = 1.243 ns; Loc. = CLKCTRL_G2; Fanout = 43; COMB Node = 'clk~clkctrl'
            Info: 3: + IC(0.842 ns) + CELL(0.666 ns) = 2.751 ns; Loc. = LCFF_X7_Y1_N17; Fanout = 1; REG Node = 'RxD_data[0]~reg0'
            Info: Total cell delay = 1.766 ns ( 64.19 % )
            Info: Total interconnect delay = 0.985 ns ( 35.81 % )
        Info: - Longest clock path from clock "clk" to source register is 2.754 ns
            Info: 1: + IC(0.000 ns) + CELL(1.100 ns) = 1.100 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'
            Info: 2: + IC(0.143 ns) + CELL(0.000 ns) = 1.243 ns; Loc. = CLKCTRL_G2; Fanout = 43; COMB Node = 'clk~clkctrl'
            Info: 3: + IC(0.845 ns) + CELL(0.666 ns) = 2.754 ns; Loc. = LCFF_X9_Y1_N5; Fanout = 2; REG Node = 'bit_spacing[3]'
            Info: Total cell delay = 1.766 ns (