📄 notetabs.rpt
字号:
Device-Specific Information: e:\202050603\sy10\notetabs.rpt
notetabs
** CLEAR SIGNALS **
Type Fan-out Name
LCELL 8 :47
Device-Specific Information: e:\202050603\sy10\notetabs.rpt
notetabs
** EQUATIONS **
clk : INPUT;
-- Node name is ':13' = 'counter0'
-- Equation name is 'counter0', location is LC1_A6, type is buried.
counter0 = DFFE(!counter0, GLOBAL( clk), !_LC1_A2, VCC, VCC);
-- Node name is ':12' = 'counter1'
-- Equation name is 'counter1', location is LC2_A5, type is buried.
counter1 = DFFE( _EQ001, GLOBAL( clk), !_LC1_A2, VCC, VCC);
_EQ001 = counter0 & !counter1
# !counter0 & counter1;
-- Node name is ':11' = 'counter2'
-- Equation name is 'counter2', location is LC1_A4, type is buried.
counter2 = DFFE( _EQ002, GLOBAL( clk), !_LC1_A2, VCC, VCC);
_EQ002 = !counter0 & counter2
# !counter1 & counter2
# counter0 & counter1 & !counter2;
-- Node name is ':10' = 'counter3'
-- Equation name is 'counter3', location is LC1_A3, type is buried.
counter3 = DFFE( _EQ003, GLOBAL( clk), !_LC1_A2, VCC, VCC);
_EQ003 = !counter2 & counter3
# !counter0 & counter3
# !counter1 & counter3
# counter0 & counter1 & counter2 & !counter3;
-- Node name is ':9' = 'counter4'
-- Equation name is 'counter4', location is LC1_A1, type is buried.
counter4 = DFFE( _EQ004, GLOBAL( clk), !_LC1_A2, VCC, VCC);
_EQ004 = !counter3 & counter4
# counter4 & !_LC5_A1
# counter3 & !counter4 & _LC5_A1;
-- Node name is ':8' = 'counter5'
-- Equation name is 'counter5', location is LC4_A1, type is buried.
counter5 = DFFE( _EQ005, GLOBAL( clk), !_LC1_A2, VCC, VCC);
_EQ005 = !counter4 & counter5
# !counter3 & counter5
# counter5 & !_LC5_A1
# counter3 & counter4 & !counter5 & _LC5_A1;
-- Node name is ':7' = 'counter6'
-- Equation name is 'counter6', location is LC8_A1, type is buried.
counter6 = DFFE( _EQ006, GLOBAL( clk), !_LC1_A2, VCC, VCC);
_EQ006 = !counter5 & counter6
# counter6 & !_LC2_A1
# counter5 & !counter6 & _LC2_A1;
-- Node name is ':6' = 'counter7'
-- Equation name is 'counter7', location is LC3_A1, type is buried.
counter7 = DFFE( _EQ007, GLOBAL( clk), !_LC1_A2, VCC, VCC);
_EQ007 = !counter6 & counter7
# !counter5 & counter7
# counter7 & !_LC2_A1
# counter5 & counter6 & !counter7 & _LC2_A1;
-- Node name is 'toneindex0'
-- Equation name is 'toneindex0', type is output
toneindex0 = _EC5_A;
-- Node name is 'toneindex1'
-- Equation name is 'toneindex1', type is output
toneindex1 = _EC10_A;
-- Node name is 'toneindex2'
-- Equation name is 'toneindex2', type is output
toneindex2 = _EC4_A;
-- Node name is 'toneindex3'
-- Equation name is 'toneindex3', type is output
toneindex3 = _EC9_A;
-- Node name is '|LPM_ADD_SUB:96|addcore:adder|:125' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC5_A1', type is buried
_LC5_A1 = LCELL( _EQ008);
_EQ008 = counter0 & counter1 & counter2;
-- Node name is '|LPM_ADD_SUB:96|addcore:adder|:133' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC2_A1', type is buried
_LC2_A1 = LCELL( _EQ009);
_EQ009 = counter3 & counter4 & _LC5_A1;
-- Node name is '~47~1'
-- Equation name is '~47~1', location is LC2_A2, type is buried.
-- synthesized logic cell
_LC2_A2 = LCELL( _EQ010);
_EQ010 = !counter1
# counter2
# !counter3;
-- Node name is '~47~2'
-- Equation name is '~47~2', location is LC3_A2, type is buried.
-- synthesized logic cell
_LC3_A2 = LCELL( _EQ011);
_EQ011 = counter5
# counter6
# !counter7;
-- Node name is ':47'
-- Equation name is '_LC1_A2', type is buried
!_LC1_A2 = _LC1_A2~NOT;
_LC1_A2~NOT = LCELL( _EQ012);
_EQ012 = counter0
# _LC2_A2
# counter4
# _LC3_A2;
-- Node name is '|music:u1|LPM_ROM:1|altrom:srom|segment0_0' from file "altrom.tdf" line 92, column 11
-- Equation name is '_EC5_A', type is memory
_EC5_A = MEMORY_SEGMENT( VCC, GLOBAL( clk), VCC, GND, VCC, counter0, counter1, counter2, counter3, counter4, counter5, counter6, counter7, VCC, VCC, VCC, counter0, counter1, counter2, counter3, counter4, counter5, counter6, counter7, VCC, VCC, VCC, VCC, VCC, VCC);
-- Node name is '|music:u1|LPM_ROM:1|altrom:srom|segment0_1' from file "altrom.tdf" line 92, column 11
-- Equation name is '_EC10_A', type is memory
_EC10_A = MEMORY_SEGMENT( VCC, GLOBAL( clk), VCC, GND, VCC, counter0, counter1, counter2, counter3, counter4, counter5, counter6, counter7, VCC, VCC, VCC, counter0, counter1, counter2, counter3, counter4, counter5, counter6, counter7, VCC, VCC, VCC, VCC, VCC, VCC);
-- Node name is '|music:u1|LPM_ROM:1|altrom:srom|segment0_2' from file "altrom.tdf" line 92, column 11
-- Equation name is '_EC4_A', type is memory
_EC4_A = MEMORY_SEGMENT( VCC, GLOBAL( clk), VCC, GND, VCC, counter0, counter1, counter2, counter3, counter4, counter5, counter6, counter7, VCC, VCC, VCC, counter0, counter1, counter2, counter3, counter4, counter5, counter6, counter7, VCC, VCC, VCC, VCC, VCC, VCC);
-- Node name is '|music:u1|LPM_ROM:1|altrom:srom|segment0_3' from file "altrom.tdf" line 92, column 11
-- Equation name is '_EC9_A', type is memory
_EC9_A = MEMORY_SEGMENT( VCC, GLOBAL( clk), VCC, GND, VCC, counter0, counter1, counter2, counter3, counter4, counter5, counter6, counter7, VCC, VCC, VCC, counter0, counter1, counter2, counter3, counter4, counter5, counter6, counter7, VCC, VCC, VCC, VCC, VCC, VCC);
Project Information e:\202050603\sy10\notetabs.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'ACEX1K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = off
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:01
Timing SNF Extractor 00:00:00
Assembler 00:00:01
-------------------------- --------
Total Time 00:00:02
Memory Allocated
-----------------
Peak memory allocated during compilation = 47,207K
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -