📄 speakera.rpt
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-- Node name is ':19' = 'c42'
-- Equation name is 'c42', location is LC3_B28, type is buried.
c42 = DFFE( _EQ002, GLOBAL( clk), !_LC1_B28, VCC, VCC);
_EQ002 = !c40 & c42
# !c41 & c42
# c40 & c41 & !c42;
-- Node name is ':18' = 'c43'
-- Equation name is 'c43', location is LC2_B28, type is buried.
c43 = DFFE( _EQ003, GLOBAL( clk), !_LC1_B28, VCC, VCC);
_EQ003 = !c42 & c43
# !c40 & c43
# !c41 & c43
# c40 & c41 & c42 & !c43;
-- Node name is ':83' = 'c110'
-- Equation name is 'c110', location is LC1_B31, type is buried.
c110 = DFFE( _EQ004, _LC1_B28, VCC, VCC, VCC);
_EQ004 = !c110
# _LC1_B27 & tone0;
-- Node name is ':82' = 'c111'
-- Equation name is 'c111', location is LC5_B30, type is buried.
c111 = DFFE( _EQ005, _LC1_B28, VCC, VCC, VCC);
_EQ005 = c110 & !c111 & !_LC1_B27
# !c110 & c111 & !_LC1_B27
# _LC1_B27 & tone1;
-- Node name is ':81' = 'c112'
-- Equation name is 'c112', location is LC4_B30, type is buried.
c112 = DFFE( _EQ006, _LC1_B28, VCC, VCC, VCC);
_EQ006 = c112 & !_LC1_B27 & !_LC8_B30
# !c112 & !_LC1_B27 & _LC8_B30
# _LC1_B27 & tone2;
-- Node name is ':80' = 'c113'
-- Equation name is 'c113', location is LC3_B30, type is buried.
c113 = DFFE( _EQ007, _LC1_B28, VCC, VCC, VCC);
_EQ007 = c113 & !_LC1_B27 & !_LC7_B30
# !c113 & !_LC1_B27 & _LC7_B30
# _LC1_B27 & tone3;
-- Node name is ':79' = 'c114'
-- Equation name is 'c114', location is LC2_B30, type is buried.
c114 = DFFE( _EQ008, _LC1_B28, VCC, VCC, VCC);
_EQ008 = c114 & !_LC1_B27 & !_LC6_B30
# !c114 & !_LC1_B27 & _LC6_B30
# _LC1_B27 & tone4;
-- Node name is ':78' = 'c115'
-- Equation name is 'c115', location is LC4_B29, type is buried.
c115 = DFFE( _EQ009, _LC1_B28, VCC, VCC, VCC);
_EQ009 = c115 & !_LC1_B27 & !_LC1_B30
# !c115 & !_LC1_B27 & _LC1_B30
# _LC1_B27 & tone5;
-- Node name is ':77' = 'c116'
-- Equation name is 'c116', location is LC3_B29, type is buried.
c116 = DFFE( _EQ010, _LC1_B28, VCC, VCC, VCC);
_EQ010 = c116 & !_LC1_B27 & !_LC6_B29
# !c116 & !_LC1_B27 & _LC6_B29
# _LC1_B27 & tone6;
-- Node name is ':76' = 'c117'
-- Equation name is 'c117', location is LC2_B29, type is buried.
c117 = DFFE( _EQ011, _LC1_B28, VCC, VCC, VCC);
_EQ011 = c117 & !_LC1_B27 & !_LC5_B29
# !c117 & !_LC1_B27 & _LC5_B29
# _LC1_B27 & tone7;
-- Node name is ':75' = 'c118'
-- Equation name is 'c118', location is LC3_B27, type is buried.
c118 = DFFE( _EQ012, _LC1_B28, VCC, VCC, VCC);
_EQ012 = c118 & !_LC1_B27 & !_LC1_B29
# !c118 & !_LC1_B27 & _LC1_B29
# _LC1_B27 & tone8;
-- Node name is ':74' = 'c119'
-- Equation name is 'c119', location is LC2_B27, type is buried.
c119 = DFFE( _EQ013, _LC1_B28, VCC, VCC, VCC);
_EQ013 = c119 & !_LC1_B27 & !_LC5_B27
# !c119 & !_LC1_B27 & _LC5_B27
# _LC1_B27 & tone9;
-- Node name is ':73' = 'c1110'
-- Equation name is 'c1110', location is LC4_B27, type is buried.
c1110 = DFFE( _EQ014, _LC1_B28, VCC, VCC, VCC);
_EQ014 = !c119 & c1110
# c1110 & !_LC5_B27
# c119 & !c1110 & _LC5_B27
# c1110 & tone10;
-- Node name is ':16' = 'fullspks'
-- Equation name is 'fullspks', location is LC6_B27, type is buried.
fullspks = DFFE( _EQ015, _LC1_B28, VCC, VCC, VCC);
_EQ015 = c118 & c119 & c1110 & _LC1_B29;
-- Node name is 'spks'
-- Equation name is 'spks', type is output
spks = _LC8_B27;
-- Node name is '|LPM_ADD_SUB:145|addcore:adder|:83' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC8_B30', type is buried
_LC8_B30 = LCELL( _EQ016);
_EQ016 = c110 & c111;
-- Node name is '|LPM_ADD_SUB:145|addcore:adder|:87' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC7_B30', type is buried
_LC7_B30 = LCELL( _EQ017);
_EQ017 = c112 & _LC8_B30;
-- Node name is '|LPM_ADD_SUB:145|addcore:adder|:91' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC6_B30', type is buried
_LC6_B30 = LCELL( _EQ018);
_EQ018 = c113 & _LC7_B30;
-- Node name is '|LPM_ADD_SUB:145|addcore:adder|:95' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC1_B30', type is buried
_LC1_B30 = LCELL( _EQ019);
_EQ019 = c114 & _LC6_B30;
-- Node name is '|LPM_ADD_SUB:145|addcore:adder|:99' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC6_B29', type is buried
_LC6_B29 = LCELL( _EQ020);
_EQ020 = c115 & _LC1_B30;
-- Node name is '|LPM_ADD_SUB:145|addcore:adder|:103' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC5_B29', type is buried
_LC5_B29 = LCELL( _EQ021);
_EQ021 = c116 & _LC6_B29;
-- Node name is '|LPM_ADD_SUB:145|addcore:adder|:107' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC1_B29', type is buried
_LC1_B29 = LCELL( _EQ022);
_EQ022 = c117 & _LC5_B29;
-- Node name is '|LPM_ADD_SUB:145|addcore:adder|:111' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC5_B27', type is buried
_LC5_B27 = LCELL( _EQ023);
_EQ023 = c118 & _LC1_B29;
-- Node name is ':13'
-- Equation name is '_LC8_B27', type is buried
_LC8_B27 = DFFE(!c2, fullspks, VCC, VCC, VCC);
-- Node name is ':27'
-- Equation name is '_LC1_B28', type is buried
_LC1_B28 = LCELL( _EQ024);
_EQ024 = c42 & c43;
-- Node name is ':98'
-- Equation name is '_LC1_B27', type is buried
_LC1_B27 = LCELL( _EQ025);
_EQ025 = c119 & c1110 & _LC5_B27;
Project Information e:\202050603\sy10\speakera.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'ACEX1K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = off
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:01
Fitter 00:00:01
Timing SNF Extractor 00:00:00
Assembler 00:00:01
-------------------------- --------
Total Time 00:00:03
Memory Allocated
-----------------
Peak memory allocated during compilation = 42,834K
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