📄 speakera.rpt
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Total: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 8 5 6 8 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 28/0
Device-Specific Information: e:\202050603\sy10\speakera.rpt
speakera
** INPUTS **
Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
79 - - - -- INPUT G ^ 0 0 0 0 clk
78 - - - -- INPUT ^ 0 0 0 1 tone0
182 - - - -- INPUT ^ 0 0 0 1 tone1
184 - - - -- INPUT ^ 0 0 0 1 tone2
143 - - B -- INPUT ^ 0 0 0 1 tone3
80 - - - -- INPUT ^ 0 0 0 1 tone4
183 - - - -- INPUT ^ 0 0 0 1 tone5
11 - - B -- INPUT ^ 0 0 0 1 tone6
12 - - B -- INPUT ^ 0 0 0 1 tone7
13 - - B -- INPUT ^ 0 0 0 1 tone8
147 - - B -- INPUT ^ 0 0 0 1 tone9
144 - - B -- INPUT ^ 0 0 0 1 tone10
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.
Device-Specific Information: e:\202050603\sy10\speakera.rpt
speakera
** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
142 - - B -- OUTPUT 0 1 0 0 spks
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: e:\202050603\sy10\speakera.rpt
speakera
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 8 - B 30 AND2 0 2 0 2 |LPM_ADD_SUB:145|addcore:adder|:83
- 7 - B 30 AND2 0 2 0 2 |LPM_ADD_SUB:145|addcore:adder|:87
- 6 - B 30 AND2 0 2 0 2 |LPM_ADD_SUB:145|addcore:adder|:91
- 1 - B 30 AND2 0 2 0 2 |LPM_ADD_SUB:145|addcore:adder|:95
- 6 - B 29 AND2 0 2 0 2 |LPM_ADD_SUB:145|addcore:adder|:99
- 5 - B 29 AND2 0 2 0 2 |LPM_ADD_SUB:145|addcore:adder|:103
- 1 - B 29 AND2 0 2 0 3 |LPM_ADD_SUB:145|addcore:adder|:107
- 5 - B 27 AND2 0 2 0 3 |LPM_ADD_SUB:145|addcore:adder|:111
- 8 - B 27 DFFE 0 2 1 0 :13
- 6 - B 27 DFFE 0 5 0 2 fullspks (:16)
- 2 - B 28 DFFE + 0 4 0 1 c43 (:18)
- 3 - B 28 DFFE + 0 3 0 2 c42 (:19)
- 4 - B 28 DFFE + 0 2 0 2 c41 (:20)
- 5 - B 28 DFFE + 0 1 0 3 c40 (:21)
- 1 - B 28 AND2 0 2 0 16 :27
- 4 - B 27 DFFE 1 3 0 2 c1110 (:73)
- 2 - B 27 DFFE 1 3 0 3 c119 (:74)
- 3 - B 27 DFFE 1 3 0 2 c118 (:75)
- 2 - B 29 DFFE 1 3 0 1 c117 (:76)
- 3 - B 29 DFFE 1 3 0 1 c116 (:77)
- 4 - B 29 DFFE 1 3 0 1 c115 (:78)
- 2 - B 30 DFFE 1 3 0 1 c114 (:79)
- 3 - B 30 DFFE 1 3 0 1 c113 (:80)
- 4 - B 30 DFFE 1 3 0 1 c112 (:81)
- 5 - B 30 DFFE 1 3 0 1 c111 (:82)
- 1 - B 31 DFFE 1 2 0 2 c110 (:83)
- 1 - B 27 AND2 0 3 0 10 :98
- 7 - B 27 DFFE 0 1 0 1 c2 (:252)
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
p = Packed register
Device-Specific Information: e:\202050603\sy10\speakera.rpt
speakera
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 0/208( 0%) 0/104( 0%) 0/104( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
B: 7/208( 3%) 0/104( 0%) 5/104( 4%) 6/16( 37%) 1/16( 6%) 0/16( 0%)
C: 0/208( 0%) 0/104( 0%) 0/104( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
D: 0/208( 0%) 0/104( 0%) 0/104( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
E: 0/208( 0%) 0/104( 0%) 0/104( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
F: 0/208( 0%) 0/104( 0%) 0/104( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
G: 0/208( 0%) 0/104( 0%) 0/104( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
H: 0/208( 0%) 0/104( 0%) 0/104( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
I: 0/208( 0%) 0/104( 0%) 0/104( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
J: 0/208( 0%) 0/104( 0%) 0/104( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
K: 0/208( 0%) 0/104( 0%) 0/104( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
L: 0/208( 0%) 0/104( 0%) 0/104( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
25: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
26: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
27: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
28: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
29: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
30: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
31: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
32: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
33: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
34: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
35: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
36: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
37: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
38: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
39: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
40: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
41: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
42: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
43: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
44: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
45: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
46: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
47: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
48: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
49: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
50: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
51: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
52: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: e:\202050603\sy10\speakera.rpt
speakera
** CLOCK SIGNALS **
Type Fan-out Name
LCELL 16 :27
INPUT 4 clk
DFF 2 fullspks
Device-Specific Information: e:\202050603\sy10\speakera.rpt
speakera
** CLEAR SIGNALS **
Type Fan-out Name
LCELL 16 :27
Device-Specific Information: e:\202050603\sy10\speakera.rpt
speakera
** EQUATIONS **
clk : INPUT;
tone0 : INPUT;
tone1 : INPUT;
tone2 : INPUT;
tone3 : INPUT;
tone4 : INPUT;
tone5 : INPUT;
tone6 : INPUT;
tone7 : INPUT;
tone8 : INPUT;
tone9 : INPUT;
tone10 : INPUT;
-- Node name is ':252' = 'c2'
-- Equation name is 'c2', location is LC7_B27, type is buried.
c2 = DFFE(!c2, fullspks, VCC, VCC, VCC);
-- Node name is ':21' = 'c40'
-- Equation name is 'c40', location is LC5_B28, type is buried.
c40 = DFFE(!c40, GLOBAL( clk), !_LC1_B28, VCC, VCC);
-- Node name is ':20' = 'c41'
-- Equation name is 'c41', location is LC4_B28, type is buried.
c41 = DFFE( _EQ001, GLOBAL( clk), !_LC1_B28, VCC, VCC);
_EQ001 = c40 & !c41
# !c40 & c41;
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