tonetaba.rpt

本文介绍了乐曲演奏电路的设计与实现中涉及的CPLD／FPGA可编程逻辑控件,开发环境MAX+PLUSⅡ,硬件描述语言HDL以及介绍了在MAX+PLUSⅡ的EDA 软件平台上, 一种基于FPGA 的乐曲

-- Node name is ':1168' 
-- Equation name is '_LC2_A7', type is buried 
_LC2_A7  = LCELL( _EQ039);
  _EQ039 = !_LC2_A9 & !_LC4_A23
         #  _LC1_A7 & !_LC2_A9 & !_LC2_A26;

-- Node name is ':1172' 
-- Equation name is '_LC3_A7', type is buried 
_LC3_A7  = LCELL( _EQ040);
  _EQ040 =  _LC2_A7 & !_LC3_A25
         #  _LC1_A11 & !_LC3_A25
         #  _LC1_A21;

-- Node name is '~1186~1' 
-- Equation name is '~1186~1', location is LC1_A22, type is buried.
-- synthesized logic cell 
_LC1_A22 = LCELL( _EQ041);
  _EQ041 = !_LC1_A16 & !_LC2_A10;

-- Node name is ':1187' 
-- Equation name is '_LC1_A7', type is buried 
_LC1_A7  = LCELL( _EQ042);
  _EQ042 = !_LC1_A13
         # !_LC1_A20 &  _LC1_A22 &  _LC3_A7;

-- Node name is ':1217' 
-- Equation name is '_LC8_A1', type is buried 
_LC8_A1  = LCELL( _EQ043);
  _EQ043 =  _LC2_A10
         #  _LC1_A17 &  _LC3_A1 & !_LC6_A1;

-- Node name is '~1219~1' 
-- Equation name is '~1219~1', location is LC1_A19, type is buried.
-- synthesized logic cell 
_LC1_A19 = LCELL( _EQ044);
  _EQ044 = !_LC1_A27 & !_LC2_A26;

-- Node name is '~1219~2' 
-- Equation name is '~1219~2', location is LC1_A18, type is buried.
-- synthesized logic cell 
_LC1_A18 = LCELL( _EQ045);
  _EQ045 = !_LC1_A9 & !_LC1_A15;

-- Node name is ':1229' 
-- Equation name is '_LC3_A1', type is buried 
_LC3_A1  = LCELL( _EQ046);
  _EQ046 =  _LC1_A10
         # !_LC1_A16 &  _LC5_A14 &  _LC8_A1;

-- Node name is '~1231~1' 
-- Equation name is '~1231~1', location is LC5_A14, type is buried.
-- synthesized logic cell 
_LC5_A14 = LCELL( _EQ047);
  _EQ047 = !_LC1_A20 & !_LC2_A24;

-- Node name is '~1250~1' 
-- Equation name is '~1250~1', location is LC1_A15, type is buried.
-- synthesized logic cell 
!_LC1_A15 = _LC1_A15~NOT;
_LC1_A15~NOT = LCELL( _EQ048);
  _EQ048 = !_LC1_A11 & !_LC2_A9;

-- Node name is '~1250~2' 
-- Equation name is '~1250~2', location is LC6_A1, type is buried.
-- synthesized logic cell 
!_LC6_A1 = _LC6_A1~NOT;
_LC6_A1~NOT = LCELL( _EQ049);
  _EQ049 =  _LC1_A18 &  _LC1_A19;

-- Node name is ':1271' 
-- Equation name is '_LC4_A1', type is buried 
_LC4_A1  = LCELL( _EQ050);
  _EQ050 =  _LC4_A1 &  _LC5_A1
         # !_LC1_A19 &  _LC5_A1
         # !_LC1_A18 &  _LC5_A1;

-- Node name is '~1273~1' 
-- Equation name is '~1273~1', location is LC1_A17, type is buried.
-- synthesized logic cell 
_LC1_A17 = LCELL( _EQ051);
  _EQ051 = !_LC1_A21 & !_LC3_A25;

-- Node name is '~1273~2' 
-- Equation name is '~1273~2', location is LC5_A1, type is buried.
-- synthesized logic cell 
_LC5_A1  = LCELL( _EQ052);
  _EQ052 = !_LC1_A10 &  _LC1_A17 &  _LC1_A22 &  _LC5_A14;

-- Node name is '~1283~1' 
-- Equation name is '~1283~1', location is LC2_A26, type is buried.
-- synthesized logic cell 
!_LC2_A26 = _LC2_A26~NOT;
_LC2_A26~NOT = LCELL( _EQ053);
  _EQ053 = !_LC3_A9 & !_LC4_A11;

-- Node name is ':1297' 
-- Equation name is '_LC3_A6', type is buried 
_LC3_A6  = LCELL( _EQ054);
  _EQ054 =  _LC1_A6 &  _LC1_A18
         #  _LC1_A18 & !_LC1_A19;

-- Node name is ':1313' 
-- Equation name is '_LC1_A6', type is buried 
_LC1_A6  = LCELL( _EQ055);
  _EQ055 =  _LC2_A6 &  _LC3_A6
         #  _LC2_A6 &  _LC2_A10
         # !_LC1_A17 &  _LC2_A6;

-- Node name is '~1315~1' 
-- Equation name is '~1315~1', location is LC2_A6, type is buried.
-- synthesized logic cell 
_LC2_A6  = LCELL( _EQ056);
  _EQ056 = !_LC1_A10 & !_LC1_A16 & !_LC1_A20 & !_LC2_A24;

-- Node name is ':1330' 
-- Equation name is '_LC2_A8', type is buried 
_LC2_A8  = LCELL( _EQ057);
  _EQ057 =  _LC1_A8 & !_LC1_A27 & !_LC3_A9
         # !_LC1_A27 & !_LC3_A9 &  _LC4_A11;

-- Node name is ':1339' 
-- Equation name is '_LC4_A8', type is buried 
_LC4_A8  = LCELL( _EQ058);
  _EQ058 = !_LC1_A11 &  _LC2_A8 & !_LC2_A9
         #  _LC1_A9 & !_LC1_A11 & !_LC2_A9;

-- Node name is ':1348' 
-- Equation name is '_LC3_A8', type is buried 
_LC3_A8  = LCELL( _EQ059);
  _EQ059 = !_LC2_A10 &  _LC4_A8
         # !_LC1_A17 & !_LC2_A10;

-- Node name is ':1355' 
-- Equation name is '_LC1_A8', type is buried 
_LC1_A8  = LCELL( _EQ060);
  _EQ060 =  _LC1_A13 &  _LC3_A8
         #  _LC1_A13 &  _LC1_A20
         #  _LC1_A13 &  _LC1_A16;

-- Node name is '~1357~1' 
-- Equation name is '~1357~1', location is LC1_A13, type is buried.
-- synthesized logic cell 
!_LC1_A13 = _LC1_A13~NOT;
_LC1_A13~NOT = LCELL( _EQ061);
  _EQ061 =  _LC1_A10
         #  _LC2_A24;

-- Node name is '~1375~1' 
-- Equation name is '~1375~1', location is LC4_A23, type is buried.
-- synthesized logic cell 
!_LC4_A23 = _LC4_A23~NOT;
_LC4_A23~NOT = LCELL( _EQ062);
  _EQ062 =  _LC1_A27
         #  _LC1_A9;

-- Node name is ':1375' 
-- Equation name is '_LC4_A4', type is buried 
_LC4_A4  = LCELL( _EQ063);
  _EQ063 =  _LC1_A4 & !_LC1_A9 & !_LC1_A27
         # !_LC1_A9 & !_LC1_A27 &  _LC2_A26;

-- Node name is ':1381' 
-- Equation name is '_LC3_A4', type is buried 
_LC3_A4  = LCELL( _EQ064);
  _EQ064 = !_LC1_A11 &  _LC4_A4
         # !_LC1_A11 &  _LC2_A9;

-- Node name is ':1388' 
-- Equation name is '_LC2_A4', type is buried 
_LC2_A4  = LCELL( _EQ065);
  _EQ065 = !_LC1_A21 &  _LC3_A4
         # !_LC1_A21 &  _LC3_A25
         # !_LC1_A22;

-- Node name is ':1397' 
-- Equation name is '_LC1_A4', type is buried 
_LC1_A4  = LCELL( _EQ066);
  _EQ066 = !_LC1_A10 & !_LC1_A20 &  _LC2_A4
         # !_LC1_A10 &  _LC2_A24;

-- Node name is ':1439' 
-- Equation name is '_LC1_A1', type is buried 
_LC1_A1  = LCELL( _EQ067);
  _EQ067 =  _LC1_A1 &  _LC5_A1
         # !_LC1_A19 &  _LC5_A1
         # !_LC1_A18 &  _LC5_A1;



Project Information                             e:\202050603\sy10\tonetaba.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Multi-Level

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'ACEX1K' family

      CARRY_CHAIN                         = ignore
      CARRY_CHAIN_LENGTH                  = 32
      CASCADE_CHAIN                       = ignore
      CASCADE_CHAIN_LENGTH                = 2
      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SUBFACTOR_EXTRACTION                = on
      IGNORE_SOFT_BUFFERS                 = on
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Use Quartus Fitter                        = off
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:00
   Fitter                                 00:00:01
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:01
   --------------------------             --------
   Total Time                             00:00:02


Memory Allocated
-----------------

Peak memory allocated during compilation  = 47,358K