top.tan.rpt

来自「次代码利用verilog HDL来描述的」· RPT 代码 · 共 215 行 · 第 1/2 页

; N/A   ; None         ; 2.800 ns   ; clk  ; beipin0:b|b ; clk      ;
+-------+--------------+------------+------+-------------+----------+


+-----------------------------------------------------------------------+
; tco                                                                   ;
+-------+--------------+------------+-------------+--------+------------+
; Slack ; Required tco ; Actual tco ; From        ; To     ; From Clock ;
+-------+--------------+------------+-------------+--------+------------+
; N/A   ; None         ; 18.500 ns  ; beipin1:d|b ; clkout ; clk        ;
; N/A   ; None         ; 17.600 ns  ; beipin0:b|b ; clkout ; clk        ;
; N/A   ; None         ; 17.600 ns  ; beipin0:b|d ; clkout ; clk        ;
; N/A   ; None         ; 16.900 ns  ; beipin1:d|c ; clkout ; clk        ;
; N/A   ; None         ; 16.900 ns  ; beipin1:d|d ; clkout ; clk        ;
; N/A   ; None         ; 16.400 ns  ; beipin1:d|e ; clkout ; clk        ;
; N/A   ; None         ; 16.000 ns  ; beipin0:b|c ; clkout ; clk        ;
; N/A   ; None         ; 15.500 ns  ; beipin0:b|e ; clkout ; clk        ;
+-------+--------------+------------+-------------+--------+------------+


+-------------------------------------------------------------------------+
; th                                                                      ;
+---------------+-------------+-----------+------+-------------+----------+
; Minimum Slack ; Required th ; Actual th ; From ; To          ; To Clock ;
+---------------+-------------+-----------+------+-------------+----------+
; N/A           ; None        ; 1.300 ns  ; clk  ; beipin0:b|b ; clk      ;
; N/A           ; None        ; 1.200 ns  ; clk  ; beipin1:d|b ; clk      ;
+---------------+-------------+-----------+------+-------------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
    Info: Version 7.0 Build 33 02/05/2007 SJ Web Edition
    Info: Processing started: Tue Apr 07 16:58:03 2009
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off top -c top
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk" is an undefined clock
Info: Clock "clk" has Internal fmax of 92.59 MHz between source register "fenpin:c|clk2" and destination register "beipin1:d|d" (period= 10.8 ns)
    Info: + Longest register to register delay is 1.800 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC8_B4; Fanout = 2; REG Node = 'fenpin:c|clk2'
        Info: 2: + IC(0.600 ns) + CELL(1.200 ns) = 1.800 ns; Loc. = LC4_B4; Fanout = 2; REG Node = 'beipin1:d|d'
        Info: Total cell delay = 1.200 ns ( 66.67 % )
        Info: Total interconnect delay = 0.600 ns ( 33.33 % )
    Info: - Smallest clock skew is 0.000 ns
        Info: + Shortest clock path from clock "clk" to destination register is 5.300 ns
            Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_55; Fanout = 12; CLK Node = 'clk'
            Info: 2: + IC(2.500 ns) + CELL(0.000 ns) = 5.300 ns; Loc. = LC4_B4; Fanout = 2; REG Node = 'beipin1:d|d'
            Info: Total cell delay = 2.800 ns ( 52.83 % )
            Info: Total interconnect delay = 2.500 ns ( 47.17 % )
        Info: - Longest clock path from clock "clk" to source register is 5.300 ns
            Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_55; Fanout = 12; CLK Node = 'clk'
            Info: 2: + IC(2.500 ns) + CELL(0.000 ns) = 5.300 ns; Loc. = LC8_B4; Fanout = 2; REG Node = 'fenpin:c|clk2'
            Info: Total cell delay = 2.800 ns ( 52.83 % )
            Info: Total interconnect delay = 2.500 ns ( 47.17 % )
    Info: + Micro clock to output delay of source is 1.100 ns
    Info: + Micro setup delay of destination is 2.500 ns
    Info: Delay path is controlled by inverted clocks -- if clock duty cycle is 50, fmax is divided by two
Info: tsu for register "beipin1:d|b" (data pin = "clk", clock pin = "clk") is 2.900 ns
    Info: + Longest pin to register delay is 5.700 ns
        Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_55; Fanout = 12; CLK Node = 'clk'
        Info: 2: + IC(1.700 ns) + CELL(1.200 ns) = 5.700 ns; Loc. = LC1_B5; Fanout = 2; REG Node = 'beipin1:d|b'
        Info: Total cell delay = 4.000 ns ( 70.18 % )
        Info: Total interconnect delay = 1.700 ns ( 29.82 % )
    Info: + Micro setup delay of destination is 2.500 ns
    Info: - Shortest clock path from clock "clk" to destination register is 5.300 ns
        Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_55; Fanout = 12; CLK Node = 'clk'
        Info: 2: + IC(2.500 ns) + CELL(0.000 ns) = 5.300 ns; Loc. = LC1_B5; Fanout = 2; REG Node = 'beipin1:d|b'
        Info: Total cell delay = 2.800 ns ( 52.83 % )
        Info: Total interconnect delay = 2.500 ns ( 47.17 % )
Info: tco from clock "clk" to destination pin "clkout" through register "beipin1:d|b" is 18.500 ns
    Info: + Longest clock path from clock "clk" to source register is 5.300 ns
        Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_55; Fanout = 12; CLK Node = 'clk'
        Info: 2: + IC(2.500 ns) + CELL(0.000 ns) = 5.300 ns; Loc. = LC1_B5; Fanout = 2; REG Node = 'beipin1:d|b'
        Info: Total cell delay = 2.800 ns ( 52.83 % )
        Info: Total interconnect delay = 2.500 ns ( 47.17 % )
    Info: + Micro clock to output delay of source is 1.100 ns
    Info: + Longest register to pin delay is 12.100 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC1_B5; Fanout = 2; REG Node = 'beipin1:d|b'
        Info: 2: + IC(2.200 ns) + CELL(1.700 ns) = 3.900 ns; Loc. = LC1_B4; Fanout = 1; COMB Node = 'beipin1:d|dout~30'
        Info: 3: + IC(0.000 ns) + CELL(1.500 ns) = 5.400 ns; Loc. = LC2_B4; Fanout = 1; COMB Node = 'clkout~7'
        Info: 4: + IC(1.600 ns) + CELL(5.100 ns) = 12.100 ns; Loc. = PIN_91; Fanout = 0; PIN Node = 'clkout'
        Info: Total cell delay = 8.300 ns ( 68.60 % )
        Info: Total interconnect delay = 3.800 ns ( 31.40 % )
Info: th for register "beipin0:b|b" (data pin = "clk", clock pin = "clk") is 1.300 ns
    Info: + Longest clock path from clock "clk" to destination register is 5.300 ns
        Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_55; Fanout = 12; CLK Node = 'clk'
        Info: 2: + IC(2.500 ns) + CELL(0.000 ns) = 5.300 ns; Loc. = LC1_B2; Fanout = 2; REG Node = 'beipin0:b|b'
        Info: Total cell delay = 2.800 ns ( 52.83 % )
        Info: Total interconnect delay = 2.500 ns ( 47.17 % )
    Info: + Micro hold delay of destination is 1.600 ns
    Info: - Shortest pin to register delay is 5.600 ns
        Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_55; Fanout = 12; CLK Node = 'clk'
        Info: 2: + IC(1.600 ns) + CELL(1.200 ns) = 5.600 ns; Loc. = LC1_B2; Fanout = 2; REG Node = 'beipin0:b|b'
        Info: Total cell delay = 4.000 ns ( 71.43 % )
        Info: Total interconnect delay = 1.600 ns ( 28.57 % )
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning
    Info: Allocated 97 megabytes of memory during processing
    Info: Processing ended: Tue Apr 07 16:58:04 2009
    Info: Elapsed time: 00:00:01