top.map.qmsg

来自「次代码利用verilog HDL来描述的」· QMSG 代码 · 共 16 行

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.0 Build 33 02/05/2007 SJ Web Edition " "Info: Version 7.0 Build 33 02/05/2007 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Tue Apr 07 16:57:51 2009 " "Info: Processing started: Tue Apr 07 16:57:51 2009" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off top -c top " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off top -c top" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "top.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file top.v" { { "Info" "ISGN_ENTITY_NAME" "1 top " "Info: Found entity 1: top" {  } { { "top.v" "" { Text "D:/倍频/beipin_top/top.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "beipin0.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file beipin0.v" { { "Info" "ISGN_ENTITY_NAME" "1 beipin0 " "Info: Found entity 1: beipin0" {  } { { "beipin0.v" "" { Text "D:/倍频/beipin_top/beipin0.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "beipin1.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file beipin1.v" { { "Info" "ISGN_ENTITY_NAME" "1 beipin1 " "Info: Found entity 1: beipin1" {  } { { "beipin1.v" "" { Text "D:/倍频/beipin_top/beipin1.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "fenpin.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file fenpin.v" { { "Info" "ISGN_ENTITY_NAME" "1 fenpin " "Info: Found entity 1: fenpin" {  } { { "fenpin.v" "" { Text "D:/倍频/beipin_top/fenpin.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "fenpin1.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file fenpin1.v" { { "Info" "ISGN_ENTITY_NAME" "1 fenpin1 " "Info: Found entity 1: fenpin1" {  } { { "fenpin1.v" "" { Text "D:/倍频/beipin_top/fenpin1.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "top " "Info: Elaborating entity \"top\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "fenpin1 fenpin1:a " "Info: Elaborating entity \"fenpin1\" for hierarchy \"fenpin1:a\"" {  } { { "top.v" "a" { Text "D:/倍频/beipin_top/top.v" 10 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "beipin0 beipin0:b " "Info: Elaborating entity \"beipin0\" for hierarchy \"beipin0:b\"" {  } { { "top.v" "b" { Text "D:/倍频/beipin_top/top.v" 11 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "fenpin fenpin:c " "Info: Elaborating entity \"fenpin\" for hierarchy \"fenpin:c\"" {  } { { "top.v" "c" { Text "D:/倍频/beipin_top/top.v" 12 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "beipin1 beipin1:d " "Info: Elaborating entity \"beipin1\" for hierarchy \"beipin1:d\"" {  } { { "top.v" "d" { Text "D:/倍频/beipin_top/top.v" 13 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "14 " "Info: Implemented 14 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "1 " "Info: Implemented 1 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0} { "Info" "ISCL_SCL_TM_OPINS" "1 " "Info: Implemented 1 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0} { "Info" "ISCL_SCL_TM_LCELLS" "12 " "Info: Implemented 12 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 0 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "116 " "Info: Allocated 116 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0} { "Info" "IQEXE_END_BANNER_TIME" "Tue Apr 07 16:57:52 2009 " "Info: Processing ended: Tue Apr 07 16:57:52 2009" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}