top.map.summary

次代码利用verilog HDL来描述的

Analysis & Synthesis Status : Successful - Tue Apr 07 16:57:53 2009
Quartus II Version : 7.0 Build 33 02/05/2007 SJ Web Edition
Revision Name : top
Top-level Entity Name : top
Family : FLEX10K
Total logic elements : 12
Total pins : 2
Total memory bits : 0