📄 top.map.rpt
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Analysis & Synthesis report for top
Tue Apr 07 16:57:53 2009
Quartus II Version 7.0 Build 33 02/05/2007 SJ Web Edition
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Analysis & Synthesis Summary
3. Analysis & Synthesis Settings
4. Analysis & Synthesis Source Files Read
5. Analysis & Synthesis Resource Usage Summary
6. Analysis & Synthesis Resource Utilization by Entity
7. General Register Statistics
8. Analysis & Synthesis Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2007 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+----------------------------------------------------------------------+
; Analysis & Synthesis Summary ;
+-----------------------------+----------------------------------------+
; Analysis & Synthesis Status ; Successful - Tue Apr 07 16:57:53 2009 ;
; Quartus II Version ; 7.0 Build 33 02/05/2007 SJ Web Edition ;
; Revision Name ; top ;
; Top-level Entity Name ; top ;
; Family ; FLEX10K ;
; Total logic elements ; 12 ;
; Total pins ; 2 ;
; Total memory bits ; 0 ;
+-----------------------------+----------------------------------------+
+--------------------------------------------------------------------------------------------+
; Analysis & Synthesis Settings ;
+----------------------------------------------------------+-----------------+---------------+
; Option ; Setting ; Default Value ;
+----------------------------------------------------------+-----------------+---------------+
; Device ; EPF10K10TC144-4 ; ;
; Top-level entity name ; top ; top ;
; Family name ; FLEX10K ; Stratix ;
; Create Debugging Nodes for IP Cores ; Off ; Off ;
; Preserve fewer node names ; On ; On ;
; Disable OpenCore Plus hardware evaluation ; Off ; Off ;
; Verilog Version ; Verilog_2001 ; Verilog_2001 ;
; VHDL Version ; VHDL93 ; VHDL93 ;
; State Machine Processing ; Auto ; Auto ;
; Safe State Machine ; Off ; Off ;
; Extract Verilog State Machines ; On ; On ;
; Extract VHDL State Machines ; On ; On ;
; Ignore Verilog initial constructs ; Off ; Off ;
; Add Pass-Through Logic to Inferred RAMs ; On ; On ;
; NOT Gate Push-Back ; On ; On ;
; Power-Up Don't Care ; On ; On ;
; Remove Redundant Logic Cells ; Off ; Off ;
; Remove Duplicate Registers ; On ; On ;
; Ignore CARRY Buffers ; Off ; Off ;
; Ignore CASCADE Buffers ; Off ; Off ;
; Ignore GLOBAL Buffers ; Off ; Off ;
; Ignore ROW GLOBAL Buffers ; Off ; Off ;
; Ignore LCELL Buffers ; Off ; Off ;
; Ignore SOFT Buffers ; On ; On ;
; Limit AHDL Integers to 32 Bits ; Off ; Off ;
; Auto Implement in ROM ; Off ; Off ;
; Optimization Technique -- FLEX 10K/10KE/10KA/ACEX 1K ; Area ; Area ;
; Carry Chain Length -- FLEX 10K ; 32 ; 32 ;
; Cascade Chain Length ; 2 ; 2 ;
; Auto Carry Chains ; On ; On ;
; Auto Open-Drain Pins ; On ; On ;
; Auto ROM Replacement ; On ; On ;
; Auto RAM Replacement ; On ; On ;
; Auto Clock Enable Replacement ; On ; On ;
; Auto Resource Sharing ; Off ; Off ;
; Allow Any RAM Size For Recognition ; Off ; Off ;
; Allow Any ROM Size For Recognition ; Off ; Off ;
; Ignore translate_off and synthesis_off directives ; Off ; Off ;
; Show Parameter Settings Tables in Synthesis Report ; On ; On ;
; HDL message level ; Level2 ; Level2 ;
; Suppress Register Optimization Related Messages ; Off ; Off ;
; Number of Removed Registers Reported in Synthesis Report ; 100 ; 100 ;
; Use smart compilation ; Off ; Off ;
+----------------------------------------------------------+-----------------+---------------+
+------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read ;
+----------------------------------+-----------------+------------------------+------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ;
+----------------------------------+-----------------+------------------------+------------------------------+
; top.v ; yes ; User Verilog HDL File ; D:/倍频/beipin_top/top.v ;
; beipin0.v ; yes ; User Verilog HDL File ; D:/倍频/beipin_top/beipin0.v ;
; beipin1.v ; yes ; User Verilog HDL File ; D:/倍频/beipin_top/beipin1.v ;
; fenpin.v ; yes ; User Verilog HDL File ; D:/倍频/beipin_top/fenpin.v ;
; fenpin1.v ; yes ; User Verilog HDL File ; D:/倍频/beipin_top/fenpin1.v ;
+----------------------------------+-----------------+------------------------+------------------------------+
+---------------------------------------------+
; Analysis & Synthesis Resource Usage Summary ;
+--------------------------------+------------+
; Resource ; Usage ;
+--------------------------------+------------+
; Total logic elements ; 12 ;
; Total combinational functions ; 4 ;
; -- Total 4-input functions ; 2 ;
; -- Total 3-input functions ; 0 ;
; -- Total 2-input functions ; 0 ;
; -- Total 1-input functions ; 2 ;
; -- Total 0-input functions ; 0 ;
; Total registers ; 10 ;
; I/O pins ; 2 ;
; Maximum fan-out node ; clk ;
; Maximum fan-out ; 10 ;
; Total fan-out ; 28 ;
; Average fan-out ; 2.00 ;
+--------------------------------+------------+
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity ;
+----------------------------+-------------+--------------+-------------+------+--------------+-------------------+------------------+-----------------+------------+---------------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; Memory Bits ; Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ;
+----------------------------+-------------+--------------+-------------+------+--------------+-------------------+------------------+-----------------+------------+---------------------+
; |top ; 12 (1) ; 10 ; 0 ; 2 ; 2 (1) ; 8 (0) ; 2 (0) ; 0 (0) ; 0 (0) ; |top ;
; |beipin0:b| ; 4 (4) ; 4 ; 0 ; 0 ; 0 (0) ; 4 (4) ; 0 (0) ; 0 (0) ; 0 (0) ; |top|beipin0:b ;
; |beipin1:d| ; 5 (5) ; 4 ; 0 ; 0 ; 1 (1) ; 4 (4) ; 0 (0) ; 0 (0) ; 0 (0) ; |top|beipin1:d ;
; |fenpin1:a| ; 1 (1) ; 1 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 1 (1) ; 0 (0) ; 0 (0) ; |top|fenpin1:a ;
; |fenpin:c| ; 1 (1) ; 1 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 1 (1) ; 0 (0) ; 0 (0) ; |top|fenpin:c ;
+----------------------------+-------------+--------------+-------------+------+--------------+-------------------+------------------+-----------------+------------+---------------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
+------------------------------------------------------+
; General Register Statistics ;
+----------------------------------------------+-------+
; Statistic ; Value ;
+----------------------------------------------+-------+
; Total registers ; 10 ;
; Number of registers using Synchronous Clear ; 0 ;
; Number of registers using Synchronous Load ; 0 ;
; Number of registers using Asynchronous Clear ; 0 ;
; Number of registers using Asynchronous Load ; 0 ;
; Number of registers using Clock Enable ; 0 ;
; Number of registers using Preset ; 0 ;
+----------------------------------------------+-------+
+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
Info: Version 7.0 Build 33 02/05/2007 SJ Web Edition
Info: Processing started: Tue Apr 07 16:57:51 2009
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off top -c top
Info: Found 1 design units, including 1 entities, in source file top.v
Info: Found entity 1: top
Info: Found 1 design units, including 1 entities, in source file beipin0.v
Info: Found entity 1: beipin0
Info: Found 1 design units, including 1 entities, in source file beipin1.v
Info: Found entity 1: beipin1
Info: Found 1 design units, including 1 entities, in source file fenpin.v
Info: Found entity 1: fenpin
Info: Found 1 design units, including 1 entities, in source file fenpin1.v
Info: Found entity 1: fenpin1
Info: Elaborating entity "top" for the top level hierarchy
Info: Elaborating entity "fenpin1" for hierarchy "fenpin1:a"
Info: Elaborating entity "beipin0" for hierarchy "beipin0:b"
Info: Elaborating entity "fenpin" for hierarchy "fenpin:c"
Info: Elaborating entity "beipin1" for hierarchy "beipin1:d"
Info: Implemented 14 device resources after synthesis - the final resource count might be different
Info: Implemented 1 input pins
Info: Implemented 1 output pins
Info: Implemented 12 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 0 warnings
Info: Allocated 116 megabytes of memory during processing
Info: Processing ended: Tue Apr 07 16:57:52 2009
Info: Elapsed time: 00:00:01
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