piso.tan.qmsg

8位并行输入的数转换成串行输出

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "clk register register cnt\[1\] q\[7\] 420.17 MHz Internal " "Info: Clock \"clk\" Internal fmax is restricted to 420.17 MHz between source register \"cnt\[1\]\" and destination register \"q\[7\]\"" { { "Info" "ITDB_CLOCK_RATE" "clock 2.38 ns " "Info: fmax restricted to clock pin edge rate 2.38 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.272 ns + Longest register register " "Info: + Longest register to register delay is 1.272 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns cnt\[1\] 1 REG LCFF_X1_Y34_N1 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X1_Y34_N1; Fanout = 3; REG Node = 'cnt\[1\]'" {  } { { "d:/program files/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus ii/win/TimingClosureFloorplan.fld" "" "" { cnt[1] } "NODE_NAME" } } { "PiSo.vhd" "" { Text "E:/Quartus II/PiSo/PiSo.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.314 ns) + CELL(0.420 ns) 0.734 ns LessThan0~37 2 COMB LCCOMB_X1_Y34_N6 8 " "Info: 2: + IC(0.314 ns) + CELL(0.420 ns) = 0.734 ns; Loc. = LCCOMB_X1_Y34_N6; Fanout = 8; COMB Node = 'LessThan0~37'" {  } { { "d:/program files/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus ii/win/TimingClosureFloorplan.fld" "" "0.734 ns" { cnt[1] LessThan0~37 } "NODE_NAME" } } { "d:/program files/quartus ii/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/program files/quartus ii/libraries/vhdl/synopsys/syn_arit.vhd" 1621 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.304 ns) + CELL(0.150 ns) 1.188 ns q~574 3 COMB LCCOMB_X1_Y34_N16 1 " "Info: 3: + IC(0.304 ns) + CELL(0.150 ns) = 1.188 ns; Loc. = LCCOMB_X1_Y34_N16; Fanout = 1; COMB Node = 'q~574'" {  } { { "d:/program files/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus ii/win/TimingClosureFloorplan.fld" "" "0.454 ns" { LessThan0~37 q~574 } "NODE_NAME" } } { "PiSo.vhd" "" { Text "E:/Quartus II/PiSo/PiSo.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.084 ns) 1.272 ns q\[7\] 4 REG LCFF_X1_Y34_N17 1 " "Info: 4: + IC(0.000 ns) + CELL(0.084 ns) = 1.272 ns; Loc. = LCFF_X1_Y34_N17; Fanout = 1; REG Node = 'q\[7\]'" {  } { { "d:/program files/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus ii/win/TimingClosureFloorplan.fld" "" "0.084 ns" { q~574 q[7] } "NODE_NAME" } } { "PiSo.vhd" "" { Text "E:/Quartus II/PiSo/PiSo.vhd" 24 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.654 ns ( 51.42 % ) " "Info: Total cell delay = 0.654 ns ( 51.42 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.618 ns ( 48.58 % ) " "Info: Total interconnect delay = 0.618 ns ( 48.58 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/program files/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus ii/win/TimingClosureFloorplan.fld" "" "1.272 ns" { cnt[1] LessThan0~37 q~574 q[7] } "NODE_NAME" } } { "d:/program files/quartus ii/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/quartus ii/win/Technology_Viewer.qrui" "1.272 ns" { cnt[1] LessThan0~37 q~574 q[7] } { 0.000ns 0.314ns 0.304ns 0.000ns } { 0.000ns 0.420ns 0.150ns 0.084ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.676 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 2.676 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns clk 1 CLK PIN_P2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_P2; Fanout = 1; CLK Node = 'clk'" {  } { { "d:/program files/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus ii/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "PiSo.vhd" "" { Text "E:/Quartus II/PiSo/PiSo.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.118 ns) + CELL(0.000 ns) 1.117 ns clk~clkctrl 2 COMB CLKCTRL_G3 11 " "Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G3; Fanout = 11; COMB Node = 'clk~clkctrl'" {  } { { "d:/program files/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus ii/win/TimingClosureFloorplan.fld" "" "0.118 ns" { clk clk~clkctrl } "NODE_NAME" } } { "PiSo.vhd" "" { Text "E:/Quartus II/PiSo/PiSo.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.022 ns) + CELL(0.537 ns) 2.676 ns q\[7\] 3 REG LCFF_X1_Y34_N17 1 " "Info: 3: + IC(1.022 ns) + CELL(0.537 ns) = 2.676 ns; Loc. = LCFF_X1_Y34_N17; Fanout = 1; REG Node = 'q\[7\]'" {  } { { "d:/program files/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus ii/win/TimingClosureFloorplan.fld" "" "1.559 ns" { clk~clkctrl q[7] } "NODE_NAME" } } { "PiSo.vhd" "" { Text "E:/Quartus II/PiSo/PiSo.vhd" 24 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.536 ns ( 57.40 % ) " "Info: Total cell delay = 1.536 ns ( 57.40 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.140 ns ( 42.60 % ) " "Info: Total interconnect delay = 1.140 ns ( 42.60 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/program files/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus ii/win/TimingClosureFloorplan.fld" "" "2.676 ns" { clk clk~clkctrl q[7] } "NODE_NAME" } } { "d:/program files/quartus ii/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/quartus ii/win/Technology_Viewer.qrui" "2.676 ns" { clk clk~combout clk~clkctrl q[7] } { 0.000ns 0.000ns 0.118ns 1.022ns } { 0.000ns 0.999ns 0.000ns 0.537ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.676 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 2.676 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns clk 1 CLK PIN_P2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_P2; Fanout = 1; CLK Node = 'clk'" {  } { { "d:/program files/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus ii/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "PiSo.vhd" "" { Text "E:/Quartus II/PiSo/PiSo.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.118 ns) + CELL(0.000 ns) 1.117 ns clk~clkctrl 2 COMB CLKCTRL_G3 11 " "Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G3; Fanout = 11; COMB Node = 'clk~clkctrl'" {  } { { "d:/program files/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus ii/win/TimingClosureFloorplan.fld" "" "0.118 ns" { clk clk~clkctrl } "NODE_NAME" } } { "PiSo.vhd" "" { Text "E:/Quartus II/PiSo/PiSo.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.022 ns) + CELL(0.537 ns) 2.676 ns cnt\[1\] 3 REG LCFF_X1_Y34_N1 3 " "Info: 3: + IC(1.022 ns) + CELL(0.537 ns) = 2.676 ns; Loc. = LCFF_X1_Y34_N1; Fanout = 3; REG Node = 'cnt\[1\]'" {  } { { "d:/program files/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus ii/win/TimingClosureFloorplan.fld" "" "1.559 ns" { clk~clkctrl cnt[1] } "NODE_NAME" } } { "PiSo.vhd" "" { Text "E:/Quartus II/PiSo/PiSo.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.536 ns ( 57.40 % ) " "Info: Total cell delay = 1.536 ns ( 57.40 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.140 ns ( 42.60 % ) " "Info: Total interconnect delay = 1.140 ns ( 42.60 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/program files/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus ii/win/TimingClosureFloorplan.fld" "" "2.676 ns" { clk clk~clkctrl cnt[1] } "NODE_NAME" } } { "d:/program files/quartus ii/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/quartus ii/win/Technology_Viewer.qrui" "2.676 ns" { clk clk~combout clk~clkctrl cnt[1] } { 0.000ns 0.000ns 0.118ns 1.022ns } { 0.000ns 0.999ns 0.000ns 0.537ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/program files/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus ii/win/TimingClosureFloorplan.fld" "" "2.676 ns" { clk clk~clkctrl q[7] } "NODE_NAME" } } { "d:/program files/quartus ii/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/quartus ii/win/Technology_Viewer.qrui" "2.676 ns" { clk clk~combout clk~clkctrl q[7] } { 0.000ns 0.000ns 0.118ns 1.022ns } { 0.000ns 0.999ns 0.000ns 0.537ns } } } { "d:/program files/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus ii/win/TimingClosureFloorplan.fld" "" "2.676 ns" { clk clk~clkctrl cnt[1] } "NODE_NAME" } } { "d:/program files/quartus ii/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/quartus ii/win/Technology_Viewer.qrui" "2.676 ns" { clk clk~combout clk~clkctrl cnt[1] } { 0.000ns 0.000ns 0.118ns 1.022ns } { 0.000ns 0.999ns 0.000ns 0.537ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.250 ns + " "Info: + Micro clock to output delay of source is 0.250 ns" {  } { { "PiSo.vhd" "" { Text "E:/Quartus II/PiSo/PiSo.vhd" 17 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.036 ns + " "Info: + Micro setup delay of destination is -0.036 ns" {  } { { "PiSo.vhd" "" { Text "E:/Quartus II/PiSo/PiSo.vhd" 24 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "d:/program files/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus ii/win/TimingClosureFloorplan.fld" "" "1.272 ns" { cnt[1] LessThan0~37 q~574 q[7] } "NODE_NAME" } } { "d:/program files/quartus ii/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/quartus ii/win/Technology_Viewer.qrui" "1.272 ns" { cnt[1] LessThan0~37 q~574 q[7] } { 0.000ns 0.314ns 0.304ns 0.000ns } { 0.000ns 0.420ns 0.150ns 0.084ns } } } { "d:/program files/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus ii/win/TimingClosureFloorplan.fld" "" "2.676 ns" { clk clk~clkctrl q[7] } "NODE_NAME" } } { "d:/program files/quartus ii/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/quartus ii/win/Technology_Viewer.qrui" "2.676 ns" { clk clk~combout clk~clkctrl q[7] } { 0.000ns 0.000ns 0.118ns 1.022ns } { 0.000ns 0.999ns 0.000ns 0.537ns } } } { "d:/program files/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus ii/win/TimingClosureFloorplan.fld" "" "2.676 ns" { clk clk~clkctrl cnt[1] } "NODE_NAME" } } { "d:/program files/quartus ii/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/quartus ii/win/Technology_Viewer.qrui" "2.676 ns" { clk clk~combout clk~clkctrl cnt[1] } { 0.000ns 0.000ns 0.118ns 1.022ns } { 0.000ns 0.999ns 0.000ns 0.537ns } } }  } 0 0 "fmax restricted to %1!s! pin edge rate %2!s!. Expand message to see actual delay path." 0 0}  } { { "d:/program files/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus ii/win/TimingClosureFloorplan.fld" "" "" { q[7] } "NODE_NAME" } } { "d:/program files/quartus ii/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/quartus ii/win/Technology_Viewer.qrui" "" { q[7] } {  } {  } } } { "PiSo.vhd" "" { Text "E:/Quartus II/PiSo/PiSo.vhd" 24 -1 0 } }  } 0 0 "Clock \"%1!s!\" %7!s! fmax is restricted to %6!s! between source %2!s! \"%4!s!\" and destination %3!s! \"%5!s!\"" 0 0}
{ "Info" "ITDB_TSU_RESULT" "q\[0\] din\[0\] clk 3.469 ns register " "Info: tsu for register \"q\[0\]\" (data pin = \"din\[0\]\", clock pin = \"clk\") is 3.469 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.181 ns + Longest pin register " "Info: + Longest pin to register delay is 6.181 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.870 ns) 0.870 ns din\[0\] 1 PIN PIN_A4 1 " "Info: 1: + IC(0.000 ns) + CELL(0.870 ns) = 0.870 ns; Loc. = PIN_A4; Fanout = 1; PIN Node = 'din\[0\]'" {  } { { "d:/program files/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus ii/win/TimingClosureFloorplan.fld" "" "" { din[0] } "NODE_NAME" } } { "PiSo.vhd" "" { Text "E:/Quartus II/PiSo/PiSo.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.807 ns) + CELL(0.420 ns) 6.097 ns q\[0\]~581 2 COMB LCCOMB_X1_Y34_N12 1 " "Info: 2: + IC(4.807 ns) + CELL(0.420 ns) = 6.097 ns; Loc. = LCCOMB_X1_Y34_N12; Fanout = 1; COMB Node = 'q\[0\]~581'" {  } { { "d:/program files/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus ii/win/TimingClosureFloorplan.fld" "" "5.227 ns" { din[0] q[0]~581 } "NODE_NAME" } } { "PiSo.vhd" "" { Text "E:/Quartus II/PiSo/PiSo.vhd" 24 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.084 ns) 6.181 ns q\[0\] 3 REG LCFF_X1_Y34_N13 2 " "Info: 3: + IC(0.000 ns) + CELL(0.084 ns) = 6.181 ns; Loc. = LCFF_X1_Y34_N13; Fanout = 2; REG Node = 'q\[0\]'" {  } { { "d:/program files/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus ii/win/TimingClosureFloorplan.fld" "" "0.084 ns" { q[0]~581 q[0] } "NODE_NAME" } } { "PiSo.vhd" "" { Text "E:/Quartus II/PiSo/PiSo.vhd" 24 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.374 ns ( 22.23 % ) " "Info: Total cell delay = 1.374 ns ( 22.23 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.807 ns ( 77.77 % ) " "Info: Total interconnect delay = 4.807 ns ( 77.77 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/program files/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus ii/win/TimingClosureFloorplan.fld" "" "6.181 ns" { din[0] q[0]~581 q[0] } "NODE_NAME" } } { "d:/program files/quartus ii/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/quartus ii/win/Technology_Viewer.qrui" "6.181 ns" { din[0] din[0]~combout q[0]~581 q[0] } { 0.000ns 0.000ns 4.807ns 0.000ns } { 0.000ns 0.870ns 0.420ns 0.084ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.036 ns + " "Info: + Micro setup delay of destination is -0.036 ns" {  } { { "PiSo.vhd" "" { Text "E:/Quartus II/PiSo/PiSo.vhd" 24 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.676 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 2.676 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns clk 1 CLK PIN_P2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_P2; Fanout = 1; CLK Node = 'clk'" {  } { { "d:/program files/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus ii/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "PiSo.vhd" "" { Text "E:/Quartus II/PiSo/PiSo.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.118 ns) + CELL(0.000 ns) 1.117 ns clk~clkctrl 2 COMB CLKCTRL_G3 11 " "Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G3; Fanout = 11; COMB Node = 'clk~clkctrl'" {  } { { "d:/program files/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus ii/win/TimingClosureFloorplan.fld" "" "0.118 ns" { clk clk~clkctrl } "NODE_NAME" } } { "PiSo.vhd" "" { Text "E:/Quartus II/PiSo/PiSo.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.022 ns) + CELL(0.537 ns) 2.676 ns q\[0\] 3 REG LCFF_X1_Y34_N13 2 " "Info: 3: + IC(1.022 ns) + CELL(0.537 ns) = 2.676 ns; Loc. = LCFF_X1_Y34_N13; Fanout = 2; REG Node = 'q\[0\]'" {  } { { "d:/program files/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus ii/win/TimingClosureFloorplan.fld" "" "1.559 ns" { clk~clkctrl q[0] } "NODE_NAME" } } { "PiSo.vhd" "" { Text "E:/Quartus II/PiSo/PiSo.vhd" 24 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.536 ns ( 57.40 % ) " "Info: Total cell delay = 1.536 ns ( 57.40 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.140 ns ( 42.60 % ) " "Info: Total interconnect delay = 1.140 ns ( 42.60 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/program files/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus ii/win/TimingClosureFloorplan.fld" "" "2.676 ns" { clk clk~clkctrl q[0] } "NODE_NAME" } } { "d:/program files/quartus ii/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/quartus ii/win/Technology_Viewer.qrui" "2.676 ns" { clk clk~combout clk~clkctrl q[0] } { 0.000ns 0.000ns 0.118ns 1.022ns } { 0.000ns 0.999ns 0.000ns 0.537ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/program files/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus ii/win/TimingClosureFloorplan.fld" "" "6.181 ns" { din[0] q[0]~581 q[0] } "NODE_NAME" } } { "d:/program files/quartus ii/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/quartus ii/win/Technology_Viewer.qrui" "6.181 ns" { din[0] din[0]~combout q[0]~581 q[0] } { 0.000ns 0.000ns 4.807ns 0.000ns } { 0.000ns 0.870ns 0.420ns 0.084ns } } } { "d:/program files/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus ii/win/TimingClosureFloorplan.fld" "" "2.676 ns" { clk clk~clkctrl q[0] } "NODE_NAME" } } { "d:/program files/quartus ii/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/quartus ii/win/Technology_Viewer.qrui" "2.676 ns" { clk clk~combout clk~clkctrl q[0] } { 0.000ns 0.000ns 0.118ns 1.022ns } { 0.000ns 0.999ns 0.000ns 0.537ns } } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk dout q\[7\] 6.398 ns register " "Info: tco from clock \"clk\" to destination pin \"dout\" through register \"q\[7\]\" is 6.398 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.676 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 2.676 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns clk 1 CLK PIN_P2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_P2; Fanout = 1; CLK Node = 'clk'" {  } { { "d:/program files/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus ii/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "PiSo.vhd" "" { Text "E:/Quartus II/PiSo/PiSo.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.118 ns) + CELL(0.000 ns) 1.117 ns clk~clkctrl 2 COMB CLKCTRL_G3 11 " "Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G3; Fanout = 11; COMB Node = 'clk~clkctrl'" {  } { { "d:/program files/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus ii/win/TimingClosureFloorplan.fld" "" "0.118 ns" { clk clk~clkctrl } "NODE_NAME" } } { "PiSo.vhd" "" { Text "E:/Quartus II/PiSo/PiSo.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.022 ns) + CELL(0.537 ns) 2.676 ns q\[7\] 3 REG LCFF_X1_Y34_N17 1 " "Info: 3: + IC(1.022 ns) + CELL(0.537 ns) = 2.676 ns; Loc. = LCFF_X1_Y34_N17; Fanout = 1; REG Node = 'q\[7\]'" {  } { { "d:/program files/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus ii/win/TimingClosureFloorplan.fld" "" "1.559 ns" { clk~clkctrl q[7] } "NODE_NAME" } } { "PiSo.vhd" "" { Text "E:/Quartus II/PiSo/PiSo.vhd" 24 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.536 ns ( 57.40 % ) " "Info: Total cell delay = 1.536 ns ( 57.40 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.140 ns ( 42.60 % ) " "Info: Total interconnect delay = 1.140 ns ( 42.60 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/program files/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus ii/win/TimingClosureFloorplan.fld" "" "2.676 ns" { clk clk~clkctrl q[7] } "NODE_NAME" } } { "d:/program files/quartus ii/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/quartus ii/win/Technology_Viewer.qrui" "2.676 ns" { clk clk~combout clk~clkctrl q[7] } { 0.000ns 0.000ns 0.118ns 1.022ns } { 0.000ns 0.999ns 0.000ns 0.537ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.250 ns + " "Info: + Micro clock to output delay of source is 0.250 ns" {  } { { "PiSo.vhd" "" { Text "E:/Quartus II/PiSo/PiSo.vhd" 24 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.472 ns + Longest register pin " "Info: + Longest register to pin delay is 3.472 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns q\[7\] 1 REG LCFF_X1_Y34_N17 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X1_Y34_N17; Fanout = 1; REG Node = 'q\[7\]'" {  } { { "d:/program files/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus ii/win/TimingClosureFloorplan.fld" "" "" { q[7] } "NODE_NAME" } } { "PiSo.vhd" "" { Text "E:/Quartus II/PiSo/PiSo.vhd" 24 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.683 ns) + CELL(2.789 ns) 3.472 ns dout 2 PIN PIN_F6 0 " "Info: 2: + IC(0.683 ns) + CELL(2.789 ns) = 3.472 ns; Loc. = PIN_F6; Fanout = 0; PIN Node = 'dout'" {  } { { "d:/program files/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus ii/win/TimingClosureFloorplan.fld" "" "3.472 ns" { q[7] dout } "NODE_NAME" } } { "PiSo.vhd" "" { Text "E:/Quartus II/PiSo/PiSo.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.789 ns ( 80.33 % ) " "Info: Total cell delay = 2.789 ns ( 80.33 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.683 ns ( 19.67 % ) " "Info: Total interconnect delay = 0.683 ns ( 19.67 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/program files/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus ii/win/TimingClosureFloorplan.fld" "" "3.472 ns" { q[7] dout } "NODE_NAME" } } { "d:/program files/quartus ii/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/quartus ii/win/Technology_Viewer.qrui" "3.472 ns" { q[7] dout } { 0.000ns 0.683ns } { 0.000ns 2.789ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/program files/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus ii/win/TimingClosureFloorplan.fld" "" "2.676 ns" { clk clk~clkctrl q[7] } "NODE_NAME" } } { "d:/program files/quartus ii/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/quartus ii/win/Technology_Viewer.qrui" "2.676 ns" { clk clk~combout clk~clkctrl q[7] } { 0.000ns 0.000ns 0.118ns 1.022ns } { 0.000ns 0.999ns 0.000ns 0.537ns } } } { "d:/program files/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus ii/win/TimingClosureFloorplan.fld" "" "3.472 ns" { q[7] dout } "NODE_NAME" } } { "d:/program files/quartus ii/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/quartus ii/win/Technology_Viewer.qrui" "3.472 ns" { q[7] dout } { 0.000ns 0.683ns } { 0.000ns 2.789ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "ITDB_TH_RESULT" "q\[7\] din\[7\] clk -0.074 ns register " "Info: th for register \"q\[7\]\" (data pin = \"din\[7\]\", clock pin = \"clk\") is -0.074 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.676 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 2.676 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns clk 1 CLK PIN_P2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_P2; Fanout = 1; CLK Node = 'clk'" {  } { { "d:/program files/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus ii/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "PiSo.vhd" "" { Text "E:/Quartus II/PiSo/PiSo.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.118 ns) + CELL(0.000 ns) 1.117 ns clk~clkctrl 2 COMB CLKCTRL_G3 11 " "Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G3; Fanout = 11; COMB Node = 'clk~clkctrl'" {  } { { "d:/program files/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus ii/win/TimingClosureFloorplan.fld" "" "0.118 ns" { clk clk~clkctrl } "NODE_NAME" } } { "PiSo.vhd" "" { Text "E:/Quartus II/PiSo/PiSo.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.022 ns) + CELL(0.537 ns) 2.676 ns q\[7\] 3 REG LCFF_X1_Y34_N17 1 " "Info: 3: + IC(1.022 ns) + CELL(0.537 ns) = 2.676 ns; Loc. = LCFF_X1_Y34_N17; Fanout = 1; REG Node = 'q\[7\]'" {  } { { "d:/program files/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus ii/win/TimingClosureFloorplan.fld" "" "1.559 ns" { clk~clkctrl q[7] } "NODE_NAME" } } { "PiSo.vhd" "" { Text "E:/Quartus II/PiSo/PiSo.vhd" 24 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.536 ns ( 57.40 % ) " "Info: Total cell delay = 1.536 ns ( 57.40 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.140 ns ( 42.60 % ) " "Info: Total interconnect delay = 1.140 ns ( 42.60 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/program files/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus ii/win/TimingClosureFloorplan.fld" "" "2.676 ns" { clk clk~clkctrl q[7] } "NODE_NAME" } } { "d:/program files/quartus ii/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/quartus ii/win/Technology_Viewer.qrui" "2.676 ns" { clk clk~combout clk~clkctrl q[7] } { 0.000ns 0.000ns 0.118ns 1.022ns } { 0.000ns 0.999ns 0.000ns 0.537ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.266 ns + " "Info: + Micro hold delay of destination is 0.266 ns" {  } { { "PiSo.vhd" "" { Text "E:/Quartus II/PiSo/PiSo.vhd" 24 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.016 ns - Shortest pin register " "Info: - Shortest pin to register delay is 3.016 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.979 ns) 0.979 ns din\[7\] 1 PIN PIN_C13 1 " "Info: 1: + IC(0.000 ns) + CELL(0.979 ns) = 0.979 ns; Loc. = PIN_C13; Fanout = 1; PIN Node = 'din\[7\]'" {  } { { "d:/program files/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus ii/win/TimingClosureFloorplan.fld" "" "" { din[7] } "NODE_NAME" } } { "PiSo.vhd" "" { Text "E:/Quartus II/PiSo/PiSo.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.678 ns) + CELL(0.275 ns) 2.932 ns q~574 2 COMB LCCOMB_X1_Y34_N16 1 " "Info: 2: + IC(1.678 ns) + CELL(0.275 ns) = 2.932 ns; Loc. = LCCOMB_X1_Y34_N16; Fanout = 1; COMB Node = 'q~574'" {  } { { "d:/program files/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus ii/win/TimingClosureFloorplan.fld" "" "1.953 ns" { din[7] q~574 } "NODE_NAME" } } { "PiSo.vhd" "" { Text "E:/Quartus II/PiSo/PiSo.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.084 ns) 3.016 ns q\[7\] 3 REG LCFF_X1_Y34_N17 1 " "Info: 3: + IC(0.000 ns) + CELL(0.084 ns) = 3.016 ns; Loc. = LCFF_X1_Y34_N17; Fanout = 1; REG Node = 'q\[7\]'" {  } { { "d:/program files/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus ii/win/TimingClosureFloorplan.fld" "" "0.084 ns" { q~574 q[7] } "NODE_NAME" } } { "PiSo.vhd" "" { Text "E:/Quartus II/PiSo/PiSo.vhd" 24 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.338 ns ( 44.36 % ) " "Info: Total cell delay = 1.338 ns ( 44.36 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.678 ns ( 55.64 % ) " "Info: Total interconnect delay = 1.678 ns ( 55.64 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/program files/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus ii/win/TimingClosureFloorplan.fld" "" "3.016 ns" { din[7] q~574 q[7] } "NODE_NAME" } } { "d:/program files/quartus ii/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/quartus ii/win/Technology_Viewer.qrui" "3.016 ns" { din[7] din[7]~combout q~574 q[7] } { 0.000ns 0.000ns 1.678ns 0.000ns } { 0.000ns 0.979ns 0.275ns 0.084ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/program files/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus ii/win/TimingClosureFloorplan.fld" "" "2.676 ns" { clk clk~clkctrl q[7] } "NODE_NAME" } } { "d:/program files/quartus ii/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/quartus ii/win/Technology_Viewer.qrui" "2.676 ns" { clk clk~combout clk~clkctrl q[7] } { 0.000ns 0.000ns 0.118ns 1.022ns } { 0.000ns 0.999ns 0.000ns 0.537ns } } } { "d:/program files/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus ii/win/TimingClosureFloorplan.fld" "" "3.016 ns" { din[7] q~574 q[7] } "NODE_NAME" } } { "d:/program files/quartus ii/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/quartus ii/win/Technology_Viewer.qrui" "3.016 ns" { din[7] din[7]~combout q~574 q[7] } { 0.000ns 0.000ns 1.678ns 0.000ns } { 0.000ns 0.979ns 0.275ns 0.084ns } } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}