piso.tan.rpt

8位并行输入的数转换成串行输出

; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; cnt[2] ; cnt[2] ; clk        ; clk      ; None                        ; None                      ; 0.407 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; q[0]   ; q[0]   ; clk        ; clk      ; None                        ; None                      ; 0.407 ns                ;
+-------+------------------------------------------------+--------+--------+------------+----------+-----------------------------+---------------------------+-------------------------+


+--------------------------------------------------------------+
; tsu                                                          ;
+-------+--------------+------------+--------+------+----------+
; Slack ; Required tsu ; Actual tsu ; From   ; To   ; To Clock ;
+-------+--------------+------------+--------+------+----------+
; N/A   ; None         ; 3.469 ns   ; din[0] ; q[0] ; clk      ;
; N/A   ; None         ; 3.357 ns   ; din[3] ; q[3] ; clk      ;
; N/A   ; None         ; 3.226 ns   ; din[4] ; q[4] ; clk      ;
; N/A   ; None         ; 3.141 ns   ; din[2] ; q[2] ; clk      ;
; N/A   ; None         ; 3.140 ns   ; din[1] ; q[1] ; clk      ;
; N/A   ; None         ; 2.936 ns   ; din[5] ; q[5] ; clk      ;
; N/A   ; None         ; 0.609 ns   ; din[6] ; q[6] ; clk      ;
; N/A   ; None         ; 0.304 ns   ; din[7] ; q[7] ; clk      ;
+-------+--------------+------------+--------+------+----------+


+--------------------------------------------------------------+
; tco                                                          ;
+-------+--------------+------------+------+------+------------+
; Slack ; Required tco ; Actual tco ; From ; To   ; From Clock ;
+-------+--------------+------------+------+------+------------+
; N/A   ; None         ; 6.398 ns   ; q[7] ; dout ; clk        ;
+-------+--------------+------------+------+------+------------+


+--------------------------------------------------------------------+
; th                                                                 ;
+---------------+-------------+-----------+--------+------+----------+
; Minimum Slack ; Required th ; Actual th ; From   ; To   ; To Clock ;
+---------------+-------------+-----------+--------+------+----------+
; N/A           ; None        ; -0.074 ns ; din[7] ; q[7] ; clk      ;
; N/A           ; None        ; -0.379 ns ; din[6] ; q[6] ; clk      ;
; N/A           ; None        ; -2.706 ns ; din[5] ; q[5] ; clk      ;
; N/A           ; None        ; -2.910 ns ; din[1] ; q[1] ; clk      ;
; N/A           ; None        ; -2.911 ns ; din[2] ; q[2] ; clk      ;
; N/A           ; None        ; -2.996 ns ; din[4] ; q[4] ; clk      ;
; N/A           ; None        ; -3.127 ns ; din[3] ; q[3] ; clk      ;
; N/A           ; None        ; -3.239 ns ; din[0] ; q[0] ; clk      ;
+---------------+-------------+-----------+--------+------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 6.0 Build 178 04/27/2006 SJ Web Edition
    Info: Processing started: Sun Mar 29 17:48:41 2009
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off PiSo -c PiSo --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk" is an undefined clock
Info: Clock "clk" Internal fmax is restricted to 420.17 MHz between source register "cnt[1]" and destination register "q[7]"
    Info: fmax restricted to clock pin edge rate 2.38 ns. Expand message to see actual delay path.
        Info: + Longest register to register delay is 1.272 ns
            Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X1_Y34_N1; Fanout = 3; REG Node = 'cnt[1]'
            Info: 2: + IC(0.314 ns) + CELL(0.420 ns) = 0.734 ns; Loc. = LCCOMB_X1_Y34_N6; Fanout = 8; COMB Node = 'LessThan0~37'
            Info: 3: + IC(0.304 ns) + CELL(0.150 ns) = 1.188 ns; Loc. = LCCOMB_X1_Y34_N16; Fanout = 1; COMB Node = 'q~574'
            Info: 4: + IC(0.000 ns) + CELL(0.084 ns) = 1.272 ns; Loc. = LCFF_X1_Y34_N17; Fanout = 1; REG Node = 'q[7]'
            Info: Total cell delay = 0.654 ns ( 51.42 % )
            Info: Total interconnect delay = 0.618 ns ( 48.58 % )
        Info: - Smallest clock skew is 0.000 ns
            Info: + Shortest clock path from clock "clk" to destination register is 2.676 ns
                Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_P2; Fanout = 1; CLK Node = 'clk'
                Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G3; Fanout = 11; COMB Node = 'clk~clkctrl'
                Info: 3: + IC(1.022 ns) + CELL(0.537 ns) = 2.676 ns; Loc. = LCFF_X1_Y34_N17; Fanout = 1; REG Node = 'q[7]'
                Info: Total cell delay = 1.536 ns ( 57.40 % )
                Info: Total interconnect delay = 1.140 ns ( 42.60 % )
            Info: - Longest clock path from clock "clk" to source register is 2.676 ns
                Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_P2; Fanout = 1; CLK Node = 'clk'
                Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G3; Fanout = 11; COMB Node = 'clk~clkctrl'
                Info: 3: + IC(1.022 ns) + CELL(0.537 ns) = 2.676 ns; Loc. = LCFF_X1_Y34_N1; Fanout = 3; REG Node = 'cnt[1]'
                Info: Total cell delay = 1.536 ns ( 57.40 % )
                Info: Total interconnect delay = 1.140 ns ( 42.60 % )
        Info: + Micro clock to output delay of source is 0.250 ns
        Info: + Micro setup delay of destination is -0.036 ns
Info: tsu for register "q[0]" (data pin = "din[0]", clock pin = "clk") is 3.469 ns
    Info: + Longest pin to register delay is 6.181 ns
        Info: 1: + IC(0.000 ns) + CELL(0.870 ns) = 0.870 ns; Loc. = PIN_A4; Fanout = 1; PIN Node = 'din[0]'
        Info: 2: + IC(4.807 ns) + CELL(0.420 ns) = 6.097 ns; Loc. = LCCOMB_X1_Y34_N12; Fanout = 1; COMB Node = 'q[0]~581'
        Info: 3: + IC(0.000 ns) + CELL(0.084 ns) = 6.181 ns; Loc. = LCFF_X1_Y34_N13; Fanout = 2; REG Node = 'q[0]'
        Info: Total cell delay = 1.374 ns ( 22.23 % )
        Info: Total interconnect delay = 4.807 ns ( 77.77 % )
    Info: + Micro setup delay of destination is -0.036 ns
    Info: - Shortest clock path from clock "clk" to destination register is 2.676 ns
        Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_P2; Fanout = 1; CLK Node = 'clk'
        Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G3; Fanout = 11; COMB Node = 'clk~clkctrl'
        Info: 3: + IC(1.022 ns) + CELL(0.537 ns) = 2.676 ns; Loc. = LCFF_X1_Y34_N13; Fanout = 2; REG Node = 'q[0]'
        Info: Total cell delay = 1.536 ns ( 57.40 % )
        Info: Total interconnect delay = 1.140 ns ( 42.60 % )
Info: tco from clock "clk" to destination pin "dout" through register "q[7]" is 6.398 ns
    Info: + Longest clock path from clock "clk" to source register is 2.676 ns
        Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_P2; Fanout = 1; CLK Node = 'clk'
        Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G3; Fanout = 11; COMB Node = 'clk~clkctrl'
        Info: 3: + IC(1.022 ns) + CELL(0.537 ns) = 2.676 ns; Loc. = LCFF_X1_Y34_N17; Fanout = 1; REG Node = 'q[7]'
        Info: Total cell delay = 1.536 ns ( 57.40 % )
        Info: Total interconnect delay = 1.140 ns ( 42.60 % )
    Info: + Micro clock to output delay of source is 0.250 ns
    Info: + Longest register to pin delay is 3.472 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X1_Y34_N17; Fanout = 1; REG Node = 'q[7]'
        Info: 2: + IC(0.683 ns) + CELL(2.789 ns) = 3.472 ns; Loc. = PIN_F6; Fanout = 0; PIN Node = 'dout'
        Info: Total cell delay = 2.789 ns ( 80.33 % )
        Info: Total interconnect delay = 0.683 ns ( 19.67 % )
Info: th for register "q[7]" (data pin = "din[7]", clock pin = "clk") is -0.074 ns
    Info: + Longest clock path from clock "clk" to destination register is 2.676 ns
        Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_P2; Fanout = 1; CLK Node = 'clk'
        Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G3; Fanout = 11; COMB Node = 'clk~clkctrl'
        Info: 3: + IC(1.022 ns) + CELL(0.537 ns) = 2.676 ns; Loc. = LCFF_X1_Y34_N17; Fanout = 1; REG Node = 'q[7]'
        Info: Total cell delay = 1.536 ns ( 57.40 % )
        Info: Total interconnect delay = 1.140 ns ( 42.60 % )
    Info: + Micro hold delay of destination is 0.266 ns
    Info: - Shortest pin to register delay is 3.016 ns
        Info: 1: + IC(0.000 ns) + CELL(0.979 ns) = 0.979 ns; Loc. = PIN_C13; Fanout = 1; PIN Node = 'din[7]'
        Info: 2: + IC(1.678 ns) + CELL(0.275 ns) = 2.932 ns; Loc. = LCCOMB_X1_Y34_N16; Fanout = 1; COMB Node = 'q~574'
        Info: 3: + IC(0.000 ns) + CELL(0.084 ns) = 3.016 ns; Loc. = LCFF_X1_Y34_N17; Fanout = 1; REG Node = 'q[7]'
        Info: Total cell delay = 1.338 ns ( 44.36 % )
        Info: Total interconnect delay = 1.678 ns ( 55.64 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning
    Info: Processing ended: Sun Mar 29 17:48:41 2009
    Info: Elapsed time: 00:00:00