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Timing Analyzer report for PiSo
Sun Mar 29 17:48:42 2009
Version 6.0 Build 178 04/27/2006 SJ Web Edition
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Timing Analyzer Summary
3. Timing Analyzer Settings
4. Clock Settings Summary
5. Clock Setup: 'clk'
6. tsu
7. tco
8. th
9. Timing Analyzer Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2006 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+--------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary ;
+------------------------------+-------+---------------+------------------------------------------------+--------+------+------------+----------+--------------+
; Type ; Slack ; Required Time ; Actual Time ; From ; To ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+-------+---------------+------------------------------------------------+--------+------+------------+----------+--------------+
; Worst-case tsu ; N/A ; None ; 3.469 ns ; din[0] ; q[0] ; -- ; clk ; 0 ;
; Worst-case tco ; N/A ; None ; 6.398 ns ; q[7] ; dout ; clk ; -- ; 0 ;
; Worst-case th ; N/A ; None ; -0.074 ns ; din[7] ; q[7] ; -- ; clk ; 0 ;
; Clock Setup: 'clk' ; N/A ; None ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; cnt[1] ; q[7] ; clk ; clk ; 0 ;
; Total number of failed paths ; ; ; ; ; ; ; ; 0 ;
+------------------------------+-------+---------------+------------------------------------------------+--------+------+------------+----------+--------------+
+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option ; Setting ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name ; EP2C35F672C6 ; ; ; ;
; Timing Models ; Final ; ; ; ;
; Number of source nodes to report per destination node ; 10 ; ; ; ;
; Number of destination nodes to report ; 10 ; ; ; ;
; Number of paths to report ; 200 ; ; ; ;
; Report Minimum Timing Checks ; Off ; ; ; ;
; Use Fast Timing Models ; Off ; ; ; ;
; Report IO Paths Separately ; Off ; ; ; ;
; Default hold multicycle ; Same As Multicycle ; ; ; ;
; Cut paths between unrelated clock domains ; On ; ; ; ;
; Cut off read during write signal paths ; On ; ; ; ;
; Cut off feedback from I/O pins ; On ; ; ; ;
; Report Combined Fast/Slow Timing ; Off ; ; ; ;
; Ignore Clock Settings ; Off ; ; ; ;
; Analyze latches as synchronous elements ; On ; ; ; ;
; Enable Recovery/Removal analysis ; Off ; ; ; ;
; Enable Clock Latency ; Off ; ; ; ;
; Use TimeQuest Timing Analyzer ; Off ; ; ; ;
+-------------------------------------------------------+--------------------+------+----+-------------+
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; Clock Node Name ; Clock Setting Name ; Type ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; clk ; ; User Pin ; None ; 0.000 ns ; 0.000 ns ; -- ; N/A ; N/A ; N/A ; ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'clk' ;
+-------+------------------------------------------------+--------+--------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack ; Actual fmax (period) ; From ; To ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-------+------------------------------------------------+--------+--------+------------+----------+-----------------------------+---------------------------+-------------------------+
; N/A ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; cnt[1] ; q[7] ; clk ; clk ; None ; None ; 1.272 ns ;
; N/A ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; cnt[1] ; q[6] ; clk ; clk ; None ; None ; 1.271 ns ;
; N/A ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; cnt[1] ; q[4] ; clk ; clk ; None ; None ; 1.271 ns ;
; N/A ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; cnt[1] ; q[3] ; clk ; clk ; None ; None ; 1.271 ns ;
; N/A ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; cnt[1] ; q[2] ; clk ; clk ; None ; None ; 1.271 ns ;
; N/A ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; cnt[1] ; q[5] ; clk ; clk ; None ; None ; 1.269 ns ;
; N/A ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; cnt[1] ; q[1] ; clk ; clk ; None ; None ; 1.269 ns ;
; N/A ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; cnt[1] ; q[0] ; clk ; clk ; None ; None ; 1.263 ns ;
; N/A ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; cnt[0] ; q[7] ; clk ; clk ; None ; None ; 1.093 ns ;
; N/A ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; cnt[0] ; q[6] ; clk ; clk ; None ; None ; 1.092 ns ;
; N/A ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; cnt[0] ; q[4] ; clk ; clk ; None ; None ; 1.092 ns ;
; N/A ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; cnt[0] ; q[3] ; clk ; clk ; None ; None ; 1.092 ns ;
; N/A ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; cnt[0] ; q[2] ; clk ; clk ; None ; None ; 1.092 ns ;
; N/A ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; cnt[0] ; q[5] ; clk ; clk ; None ; None ; 1.090 ns ;
; N/A ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; cnt[0] ; q[1] ; clk ; clk ; None ; None ; 1.090 ns ;
; N/A ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; cnt[0] ; q[0] ; clk ; clk ; None ; None ; 1.084 ns ;
; N/A ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; cnt[0] ; cnt[2] ; clk ; clk ; None ; None ; 1.038 ns ;
; N/A ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; cnt[2] ; q[7] ; clk ; clk ; None ; None ; 1.016 ns ;
; N/A ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; cnt[2] ; q[6] ; clk ; clk ; None ; None ; 1.015 ns ;
; N/A ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; cnt[2] ; q[4] ; clk ; clk ; None ; None ; 1.015 ns ;
; N/A ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; cnt[2] ; q[3] ; clk ; clk ; None ; None ; 1.015 ns ;
; N/A ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; cnt[2] ; q[2] ; clk ; clk ; None ; None ; 1.015 ns ;
; N/A ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; cnt[2] ; q[5] ; clk ; clk ; None ; None ; 1.013 ns ;
; N/A ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; cnt[2] ; q[1] ; clk ; clk ; None ; None ; 1.013 ns ;
; N/A ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; cnt[2] ; q[0] ; clk ; clk ; None ; None ; 1.007 ns ;
; N/A ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; q[6] ; q[7] ; clk ; clk ; None ; None ; 0.993 ns ;
; N/A ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; cnt[1] ; cnt[2] ; clk ; clk ; None ; None ; 0.917 ns ;
; N/A ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; q[0] ; q[1] ; clk ; clk ; None ; None ; 0.875 ns ;
; N/A ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; q[5] ; q[6] ; clk ; clk ; None ; None ; 0.849 ns ;
; N/A ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; q[2] ; q[3] ; clk ; clk ; None ; None ; 0.848 ns ;
; N/A ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; q[4] ; q[5] ; clk ; clk ; None ; None ; 0.841 ns ;
; N/A ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; q[1] ; q[2] ; clk ; clk ; None ; None ; 0.841 ns ;
; N/A ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; q[3] ; q[4] ; clk ; clk ; None ; None ; 0.803 ns ;
; N/A ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; cnt[0] ; cnt[1] ; clk ; clk ; None ; None ; 0.732 ns ;
; N/A ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; cnt[1] ; cnt[1] ; clk ; clk ; None ; None ; 0.407 ns ;
; N/A ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; cnt[0] ; cnt[0] ; clk ; clk ; None ; None ; 0.407 ns ;
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