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16x11-bit ROM : 1==================================================================================================================================================* Low Level Synthesis *=========================================================================Optimizing unit <ex3> ...Loading device for application Xst from file '3s200.nph' in environment C:/Xilinx.Mapping all equations...Building and optimizing final netlist ...Found area constraint ratio of 100 (+ 5) on block ex3, actual ratio is 0.=========================================================================* Final Report *=========================================================================Device utilization summary:---------------------------Selected Device : 3s200ft256-4 Number of Slices: 4 out of 1920 0% Number of 4 input LUTs: 7 out of 3840 0% Number of bonded IOBs: 11 out of 173 6% =========================================================================TIMING REPORTClock Information:------------------No clock signals found in this designTiming Summary:---------------Speed Grade: -4 Minimum period: No path found Minimum input arrival time before clock: No path found Maximum output required time after clock: No path found Maximum combinational path delay: 7.178ns=========================================================================Completed process "Synthesize".
Started process "Translate".Command Line: ngdbuild -intstyle ise -dd d:\7-segment/_ngo -uc ex3.ucf -pxc3s200-ft256-4 ex3.ngc ex3.ngd Reading NGO file "d:/7-segment/ex3.ngc" ...Reading component libraries for design expansion...Annotating constraints to design from file "ex3.ucf" ...Checking timing specifications ...Checking expanded design ...NGDBUILD Design Results Summary: Number of errors: 0 Number of warnings: 0Total memory usage is 40160 kilobytesWriting NGD file "ex3.ngd" ...Writing NGDBUILD log file "ex3.bld"...NGDBUILD done.Completed process "Translate".
Started process "Map".Using target part "3s200ft256-4".Removing unused or disabled logic...Running cover...Running directed packing...Running delay-based LUT packing...Running related packing...Design Summary:Number of errors: 0Number of warnings: 0Logic Utilization: Number of 4 input LUTs: 7 out of 3,840 1%Logic Distribution: Number of occupied Slices: 4 out of 1,920 1% Number of Slices containing only related logic: 4 out of 4 100% Number of Slices containing unrelated logic: 0 out of 4 0% *See NOTES below for an explanation of the effects of unrelated logicTotal Number of 4 input LUTs: 7 out of 3,840 1% Number of bonded IOBs: 11 out of 173 6%Total equivalent gate count for design: 42Additional JTAG gate count for IOBs: 528Peak Memory Usage: 67 MBNOTES: Related logic is defined as being logic that shares connectivity - e.g. two LUTs are "related" if they share common inputs. When assembling slices, Map gives priority to combine logic that is related. Doing so results in the best timing performance. Unrelated logic shares no connectivity. Map will only begin packing unrelated logic into a slice once 99% of the slices are occupied through related logic packing. Note that once logic distribution reaches the 99% level through related logic packing, this does not mean the device is completely utilized. Unrelated logic packing will then begin, continuing until all usable LUTs and FFs are occupied. Depending on your timing budget, increased levels of unrelated logic packing may adversely affect the overall timing performance of your design.Mapping completed.See MAP report file "ex3_map.mrp" for details.Completed process "Map".Mapping Module ex3 . . .
MAP command line:
map -intstyle ise -p xc3s200-ft256-4 -cm area -pr b -k 4 -c 100 -tx off -o ex3_map.ncd ex3.ngd ex3.pcf
Mapping Module ex3: DONE
Started process "Place & Route".Constraints file: ex3.pcfLoading device database for application Par from file "ex3_map.ncd". "ex3" is an NCD, version 2.38, device xc3s200, package ft256, speed -4Loading device for application Par from file '3s200.nph' in environmentC:/Xilinx.Device speed data version: ADVANCED 1.29 2003-12-13.Resolving physical constraints.Finished resolving physical constraints.Device utilization summary: Number of External IOBs 11 out of 173 6% Number of LOCed External IOBs 11 out of 11 100% Number of Slices 4 out of 1920 1%Overall effort level (-ol): Standard (set by user)Placer effort level (-pl): Standard (set by user)Placer cost table entry (-t): 1Router effort level (-rl): Standard (set by user)Phase 1.1Phase 1.1 (Checksum:98969d) REAL time: 0 secs Phase 3.8.Phase 3.8 (Checksum:98b56f) REAL time: 0 secs Phase 4.5Phase 4.5 (Checksum:26259fc) REAL time: 0 secs Phase 5.18Phase 5.18 (Checksum:2faf07b) REAL time: 0 secs Writing design to file ex3.ncd.Total REAL time to Placer completion: 0 secs Total CPU time to Placer completion: 0 secs Phase 1: 35 unrouted; REAL time: 0 secs Phase 2: 35 unrouted; REAL time: 0 secs Phase 3: 18 unrouted; REAL time: 0 secs Phase 4: 0 unrouted; REAL time: 0 secs Total REAL time to Router completion: 0 secs Total CPU time to Router completion: 0 secs Generating "par" statistics.Generating Pad Report.All signals are completely routed.Total REAL time to PAR completion: 0 secs Total CPU time to PAR completion: 0 secs Peak Memory Usage: 56 MBPlacement: Completed - No errors found.Routing: Completed - No errors found.Writing design to file ex3.ncd.PAR done.Completed process "Place & Route".Started process "Generate Post-Place & Route Static Timing".Analysis completed Thu Apr 09 13:11:11 2009--------------------------------------------------------------------------------Generating Report ...Completed process "Generate Post-Place & Route Static Timing".Place & Route Module ex3 . . .
PAR command line: par -w -intstyle ise -ol std -t 1 ex3_map.ncd ex3.ncd ex3.pcf
PAR completed successfully
Started process "Generate Programming File".Completed process "Generate Programming File".
Project Navigator Auto-Make Log File-------------------------------------
Started process "Synthesize".=========================================================================* HDL Compilation *=========================================================================WARNING:HDLParsers:3215 - Unit work/EX3 is now defined in a different file: was d:/7-segment/ex3.vhdl, now is F:/7-segment/ex3.vhdlWARNING:HDLParsers:3215 - Unit work/EX3/BEHAVIORAL is now defined in a different file: was d:/7-segment/ex3.vhdl, now is F:/7-segment/ex3.vhdlCompiling vhdl file F:/7-segment/ex3.vhdl in Library work.Architecture behavioral of Entity ex3 is up to date.=========================================================================* HDL Analysis *=========================================================================Analyzing Entity <ex3> (Architecture <behavioral>).Entity <ex3> analyzed. Unit <ex3> generated.=========================================================================* HDL Synthesis *=========================================================================Synthesizing Unit <ex3>. Related source file is F:/7-segment/ex3.vhdl. Using one-hot encoding for signal <index>. Found 16x11-bit ROM for signal <index>. Summary: inferred 1 ROM(s).Unit <ex3> synthesized.=========================================================================* Advanced HDL Synthesis *=========================================================================Advanced RAM inference ...Advanced multiplier inference ...Advanced Registered AddSub inference ...Dynamic shift register inference ...=========================================================================HDL Synthesis ReportMacro Statistics# ROMs : 1 16x11-bit ROM : 1==================================================================================================================================================* Low Level Synthesis *=========================================================================Optimizing unit <ex3> ...Loading device for application Xst from file '3s200.nph' in environment C:/Xilinx.Mapping all equations...Building and optimizing final netlist ...Found area constraint ratio of 100 (+ 5) on block ex3, actual ratio is 0.=========================================================================* Final Report *=========================================================================Device utilization summary:---------------------------Selected Device : 3s200ft256-4 Number of Slices: 4 out of 1920 0% Number of 4 input LUTs: 7 out of 3840 0% Number of bonded IOBs: 11 out of 173 6% =========================================================================TIMING REPORTClock Information:------------------No clock signals found in this designTiming Summary:---------------Speed Grade: -4 Minimum period: No path found Minimum input arrival time before clock: No path found Maximum output required time after clock: No path found Maximum combinational path delay: 8.313ns=========================================================================Completed process "Synthesize".
Started process "Translate".Command Line: ngdbuild -intstyle ise -dd f:\7-segment/_ngo -uc ex3.ucf -pxc3s200-ft256-4 ex3.ngc ex3.ngd Reading NGO file "F:/7-segment/ex3.ngc" ...Reading component libraries for design expansion...Annotating constraints to design from file "ex3.ucf" ...Checking timing specifications ...Checking expanded design ...NGDBUILD Design Results Summary: Number of errors: 0 Number of warnings: 0Total memory usage is 42028 kilobytesWriting NGD file "ex3.ngd" ...Writing NGDBUILD log file "ex3.bld"...NGDBUILD done.Completed process "Translate".
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