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Project Navigator Auto-Make Log File-------------------------------------
Started process "Synthesize".=========================================================================* HDL Compilation *=========================================================================Compiling vhdl file d:/7-segment/ex3.vhdl in Library work.ERROR:HDLParsers:164 - d:/7-segment/ex3.vhdl Line 13. parse error, unexpected TOKOUT, expecting IDENTIFIERWARNING:HDLParsers:3465 - Library as no units. Did not save reference file xst/work/hdllib.ref for it.--> Total memory usage is 48128 kilobytesERROR: XST failedProcess "Synthesize" did not complete.
Project Navigator Auto-Make Log File-------------------------------------
Started process "Check Syntax".=========================================================================* HDL Compilation *=========================================================================Compiling vhdl file d:/7-segment/ex3.vhdl in Library work.ERROR:HDLParsers:164 - d:/7-segment/ex3.vhdl Line 13. parse error, unexpected TOKOUT, expecting IDENTIFIERWARNING:HDLParsers:3465 - Library as no units. Did not save reference file xst/work/hdllib.ref for it.ERROR: XST failedProcess "Check Syntax" did not complete.
Project Navigator Auto-Make Log File-------------------------------------
Started process "Synthesize".=========================================================================* HDL Compilation *=========================================================================Compiling vhdl file d:/7-segment/ex3.vhdl in Library work.Entity <ex3> (Architecture <Behavioral>) compiled.=========================================================================* HDL Analysis *=========================================================================Analyzing Entity <ex3> (Architecture <Behavioral>).Entity <ex3> analyzed. Unit <ex3> generated.=========================================================================* HDL Synthesis *=========================================================================Synthesizing Unit <ex3>. Related source file is d:/7-segment/ex3.vhdl. Using one-hot encoding for signal <index>. Found 16x11-bit ROM for signal <index>. Summary: inferred 1 ROM(s).Unit <ex3> synthesized.=========================================================================* Advanced HDL Synthesis *=========================================================================Advanced RAM inference ...Advanced multiplier inference ...Dynamic shift register inference ...=========================================================================HDL Synthesis ReportMacro Statistics# ROMs : 1 16x11-bit ROM : 1==================================================================================================================================================* Low Level Synthesis *=========================================================================Optimizing unit <ex3> ...Loading device for application Xst from file '3s200.nph' in environment C:/Xilinx.Mapping all equations...Building and optimizing final netlist ...Found area constraint ratio of 100 (+ 5) on block ex3, actual ratio is 0.=========================================================================* Final Report *=========================================================================Device utilization summary:---------------------------Selected Device : 3s200ft256-4 Number of Slices: 4 out of 1920 0% Number of 4 input LUTs: 7 out of 3840 0% Number of bonded IOBs: 11 out of 173 6% =========================================================================TIMING REPORTClock Information:------------------No clock signals found in this designTiming Summary:---------------Speed Grade: -4 Minimum period: No path found Minimum input arrival time before clock: No path found Maximum output required time after clock: No path found Maximum combinational path delay: 7.178ns=========================================================================Completed process "Synthesize".
Project Navigator Auto-Make Log File-------------------------------------
Started process "View RTL Schematic".=========================================================================* HDL Compilation *=========================================================================Compiling vhdl file d:/7-segment/ex3.vhdl in Library work.Entity <ex3> (Architecture <behavioral>) compiled.=========================================================================* HDL Analysis *=========================================================================Analyzing Entity <ex3> (Architecture <behavioral>).Entity <ex3> analyzed. Unit <ex3> generated.=========================================================================* HDL Synthesis *=========================================================================Synthesizing Unit <ex3>. Related source file is d:/7-segment/ex3.vhdl. Using one-hot encoding for signal <index>. Found 16x11-bit ROM for signal <index>. Summary: inferred 1 ROM(s).Unit <ex3> synthesized.=========================================================================* Advanced HDL Synthesis *=========================================================================Advanced RAM inference ...Advanced multiplier inference ...Dynamic shift register inference ...=========================================================================HDL Synthesis ReportMacro Statistics# ROMs : 1 16x11-bit ROM : 1==================================================================================================================================================* Low Level Synthesis *==================================================================================================================================================* Final Report *=========================================================================Completed process "View RTL Schematic".
Project Navigator Auto-Make Log File-------------------------------------
Started process "Synthesize".=========================================================================* HDL Compilation *=========================================================================Compiling vhdl file d:/7-segment/ex3.vhdl in Library work.Architecture behavioral of Entity ex3 is up to date.=========================================================================* HDL Analysis *=========================================================================Analyzing Entity <ex3> (Architecture <behavioral>).Entity <ex3> analyzed. Unit <ex3> generated.=========================================================================* HDL Synthesis *=========================================================================Synthesizing Unit <ex3>. Related source file is d:/7-segment/ex3.vhdl. Using one-hot encoding for signal <index>. Found 16x11-bit ROM for signal <index>. Summary: inferred 1 ROM(s).Unit <ex3> synthesized.=========================================================================* Advanced HDL Synthesis *=========================================================================Advanced RAM inference ...Advanced multiplier inference ...Dynamic shift register inference ...=========================================================================HDL Synthesis ReportMacro Statistics# ROMs : 1 16x11-bit ROM : 1==================================================================================================================================================* Low Level Synthesis *=========================================================================Optimizing unit <ex3> ...Loading device for application Xst from file '3s200.nph' in environment C:/Xilinx.Mapping all equations...Building and optimizing final netlist ...Found area constraint ratio of 100 (+ 5) on block ex3, actual ratio is 0.=========================================================================* Final Report *=========================================================================Device utilization summary:---------------------------Selected Device : 3s200ft256-4 Number of Slices: 4 out of 1920 0% Number of 4 input LUTs: 7 out of 3840 0% Number of bonded IOBs: 11 out of 173 6% =========================================================================TIMING REPORTClock Information:------------------No clock signals found in this designTiming Summary:---------------Speed Grade: -4 Minimum period: No path found Minimum input arrival time before clock: No path found Maximum output required time after clock: No path found Maximum combinational path delay: 7.178ns=========================================================================Completed process "Synthesize".
Started process "Translate".Command Line: ngdbuild -intstyle ise -dd d:\7-segment/_ngo -i -p xc3s200-ft256-4ex3.ngc ex3.ngd Reading NGO file "d:/7-segment/ex3.ngc" ...Reading component libraries for design expansion...Checking timing specifications ...Checking expanded design ...NGDBUILD Design Results Summary: Number of errors: 0 Number of warnings: 0Total memory usage is 39136 kilobytesWriting NGD file "ex3.ngd" ...Writing NGDBUILD log file "ex3.bld"...NGDBUILD done.Completed process "Translate".
Project Navigator Auto-Make Log File-------------------------------------
Started process "Synthesize".=========================================================================* HDL Compilation *=========================================================================Compiling vhdl file d:/7-segment/ex3.vhdl in Library work.Entity <ex3> (Architecture <behavioral>) compiled.=========================================================================* HDL Analysis *=========================================================================Analyzing Entity <ex3> (Architecture <behavioral>).Entity <ex3> analyzed. Unit <ex3> generated.=========================================================================* HDL Synthesis *=========================================================================Synthesizing Unit <ex3>. Related source file is d:/7-segment/ex3.vhdl. Using one-hot encoding for signal <index>. Found 16x11-bit ROM for signal <index>. Summary: inferred 1 ROM(s).Unit <ex3> synthesized.=========================================================================* Advanced HDL Synthesis *=========================================================================Advanced RAM inference ...Advanced multiplier inference ...Dynamic shift register inference ...=========================================================================HDL Synthesis ReportMacro Statistics# ROMs : 1⌨️ 快捷键说明
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