ex3.vhdl

VHDL Design of BCD to 7-segment decoder using PROM

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

--  Uncomment the following lines to use the declarations that are
--  provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;

entity ex3 is
    Port ( BCD : in std_logic_vector(3 downto 0);
           myout : out std_logic_vector(6 downto 0));
end ex3;

architecture Behavioral of ex3 is

type arr is array (0 to 10) of std_logic_vector (6 downto 0);
constant ROM: arr:=("0000001","1001111","0010010","0000110","1001100","0100100","0100000","0001111","0000000","0000100","0001000");
signal index: integer range 0 to 10;
 
begin

with BCD select

index<= 0 when "0000",
         1 when "0001",
	    2 when "0010",
	    3 when "0011",
	    4 when "0100",
	    5 when "0101",
	    6 when "0110",
	    7 when "0111",
	    8 when "1000",
	    9 when "1001",
	    10 when others ;

	    myout<= ROM(index);

end Behavioral;