ex3.ucf

VHDL Design of BCD to 7-segment decoder using PROM

#PACE: Start of Constraints generated by PACE

#PACE: Start of PACE I/O Pin Assignments
NET "BCD<0>"  LOC = "H13"  ;
NET "BCD<1>"  LOC = "H14"  ;
NET "BCD<2>"  LOC = "G12"  ;
NET "BCD<3>"  LOC = "F12"  ;
NET "myout<0>"  LOC = "N16"  ;
NET "myout<1>"  LOC = "F13"  ;
NET "myout<2>"  LOC = "R16"  ;
NET "myout<3>"  LOC = "P15"  ;
NET "myout<4>"  LOC = "N15"  ;
NET "myout<5>"  LOC = "G13"  ;
NET "myout<6>"  LOC = "E14"  ;

#PACE: Start of PACE Area Constraints

#PACE: Start of PACE Prohibit Constraints

#PACE: End of Constraints generated by PACE