📄 mult4x4.rpt
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* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: e:\ajun\mult4x4.rpt
mult4x4
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'B':
Logic cells placed in LAB 'B'
+------------------------------- LC25 |LPM_ADD_SUB:617|addcore:adder|addcore:adder0|gc2~1
| +----------------------------- LC29 |LPM_ADD_SUB:617|addcore:adder|addcore:adder0|g4
| | +--------------------------- LC28 |LPM_ADD_SUB:617|addcore:adder|addcore:adder0|result_node2
| | | +------------------------- LC26 |LPM_ADD_SUB:617|addcore:adder|addcore:adder0|result_node3
| | | | +----------------------- LC24 |LPM_ADD_SUB:624|addcore:adder|addcore:adder0|g4
| | | | | +--------------------- LC31 |LPM_ADD_SUB:624|addcore:adder|addcore:adder0|ps3
| | | | | | +------------------- LC27 |LPM_ADD_SUB:624|addcore:adder|addcore:adder0|result_node3
| | | | | | | +----------------- LC17 Q1
| | | | | | | | +--------------- LC30 Q2
| | | | | | | | | +------------- LC23 ~233~1
| | | | | | | | | | +----------- LC22 ~242~1
| | | | | | | | | | | +--------- LC19 ~433~1
| | | | | | | | | | | | +------- LC32 ~442~1
| | | | | | | | | | | | | +----- LC18 ~445~1
| | | | | | | | | | | | | | +--- LC20 ~451~1
| | | | | | | | | | | | | | | +- LC21 ~454~1
| | | | | | | | | | | | | | | |
| | | | | | | | | | | | | | | | Other LABs fed by signals
| | | | | | | | | | | | | | | | that feed LAB 'B'
LC | | | | | | | | | | | | | | | | | A B C D | Logic cells that feed LAB 'B':
LC25 -> - * - * - - - - - - - - - - - - | - * - - | <-- |LPM_ADD_SUB:617|addcore:adder|addcore:adder0|gc2~1
LC28 -> - - - - * - * - * - - - - - - - | - * - - | <-- |LPM_ADD_SUB:617|addcore:adder|addcore:adder0|result_node2
LC26 -> - - - - * * * - - - - - - - - - | - * - - | <-- |LPM_ADD_SUB:617|addcore:adder|addcore:adder0|result_node3
LC31 -> - - - - * - * - - - - - - - - - | - * - - | <-- |LPM_ADD_SUB:624|addcore:adder|addcore:adder0|ps3
LC23 -> * * * - - - - - - - - - - - - - | - * - - | <-- ~233~1
LC22 -> * * * - - - - * - - - - - - - - | - * - - | <-- ~242~1
LC32 -> - - - - * * * - - - - - - * - - | - * - - | <-- ~442~1
LC18 -> - - - - - - - - - - - - * - - - | - * - - | <-- ~445~1
LC20 -> - - - - - - - - * - - - - - - * | - * - - | <-- ~451~1
LC21 -> - - - - - - - - - - - - - - * - | - * - - | <-- ~454~1
Pin
9 -> - - - - * - * - - - - - - - * - | - * * * | <-- X0
11 -> - - - - * - - - - - * - * - - - | * * - * | <-- X1
19 -> - - - - - - - - - * - * - - - - | * * * * | <-- X2
5 -> - - - - - - - - - * * - - - - - | - * * - | <-- Y0
4 -> - - - - * * * - * - - * * * * * | - * * - | <-- Y2
LC44 -> - - - - - - - - * - - - - - - - | - * - - | <-- |LPM_ADD_SUB:624|datab_node2
LC38 -> - * - * - - - - - - - - - - - - | - * - - | <-- ~224~1
LC3 -> - * - * - - - - - - - - - - - - | - * - - | <-- ~327~1
LC2 -> * * * - - - - - - - - - - - - - | - * - - | <-- ~336~1
LC36 -> * * * - - - - * - - - - - - - - | - * - - | <-- ~345~1
LC39 -> - - - - - - - - - - - * - - - - | - * - - | <-- ~436~1
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: e:\ajun\mult4x4.rpt
mult4x4
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'C':
Logic cells placed in LAB 'C'
+------------------------------- LC45 |LPM_ADD_SUB:617|addcore:adder|addcore:adder0|result_node4
| +----------------------------- LC40 |LPM_ADD_SUB:624|addcore:adder|addcore:adder0|g2cp1
| | +--------------------------- LC37 |LPM_ADD_SUB:624|addcore:adder|addcore:adder0|ps5
| | | +------------------------- LC48 |LPM_ADD_SUB:624|addcore:adder|addcore:adder0|result_node4
| | | | +----------------------- LC47 |LPM_ADD_SUB:624|addcore:adder|addcore:adder0|result_node5
| | | | | +--------------------- LC46 |LPM_ADD_SUB:624|addcore:adder|addcore:adder0|result_node6
| | | | | | +------------------- LC44 |LPM_ADD_SUB:624|datab_node2
| | | | | | | +----------------- LC43 |LPM_ADD_SUB:624|datab_node4
| | | | | | | | +--------------- LC33 Q0
| | | | | | | | | +------------- LC38 ~224~1
| | | | | | | | | | +----------- LC41 ~312~1
| | | | | | | | | | | +--------- LC42 ~318~1
| | | | | | | | | | | | +------- LC36 ~345~1
| | | | | | | | | | | | | +----- LC35 ~421~1
| | | | | | | | | | | | | | +--- LC34 ~427~1
| | | | | | | | | | | | | | | +- LC39 ~436~1
| | | | | | | | | | | | | | | |
| | | | | | | | | | | | | | | | Other LABs fed by signals
| | | | | | | | | | | | | | | | that feed LAB 'C'
LC | | | | | | | | | | | | | | | | | A B C D | Logic cells that feed LAB 'C':
LC45 -> - * - * * * - - - - - - - - - - | - - * - | <-- |LPM_ADD_SUB:617|addcore:adder|addcore:adder0|result_node4
LC40 -> - - - - - * - - - - - - - - - - | - - * - | <-- |LPM_ADD_SUB:624|addcore:adder|addcore:adder0|g2cp1
LC37 -> - * - - * * - - - - - - - - - - | - - * - | <-- |LPM_ADD_SUB:624|addcore:adder|addcore:adder0|ps5
LC43 -> - - - * * * - - - - - - - - - - | - - * - | <-- |LPM_ADD_SUB:624|datab_node4
LC41 -> - - - - * - - - - - - * - - - - | - - * - | <-- ~312~1
LC42 -> - - - - - - - - - - * - - - - - | - - * - | <-- ~318~1
LC35 -> - - * - - - - - - - - - - - * - | - - * - | <-- ~421~1
LC34 -> - - - - - - - - - - - - - * - - | - - * - | <-- ~427~1
Pin
9 -> - - - - - - * - * - - - * - - - | - * * * | <-- X0
19 -> - * - - * - - * - - - - - - - - | * * * * | <-- X2
6 -> * * * - * - - - - * * - - * - - | - - * * | <-- X3
5 -> - - - - - - - - * * - - - - - - | - * * - | <-- Y0
8 -> * * * - * - - - - - * * * - - - | * - * - | <-- Y1
4 -> - * * * * - * * - - - - - * * * | - * * - | <-- Y2
LC29 -> * * * - * - - - - - - - - - - - | - - * - | <-- |LPM_ADD_SUB:617|addcore:adder|addcore:adder0|g4
LC24 -> - - - * * * - - - - - - - - - - | - - * - | <-- |LPM_ADD_SUB:624|addcore:adder|addcore:adder0|g4
LC19 -> - - - * - - - - - - - - - - - * | - - * - | <-- ~433~1
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: e:\ajun\mult4x4.rpt
mult4x4
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'D':
Logic cells placed in LAB 'D'
+------------------------------- LC58 |LPM_ADD_SUB:632|addcore:adder|g2cp2
| +----------------------------- LC56 |LPM_ADD_SUB:632|addcore:adder|ps3
| | +--------------------------- LC62 |LPM_ADD_SUB:632|addcore:adder|ps4
| | | +------------------------- LC60 |LPM_ADD_SUB:632|datab_node6
| | | | +----------------------- LC52 Q3
| | | | | +--------------------- LC51 Q4
| | | | | | +------------------- LC49 Q5
| | | | | | | +----------------- LC64 Q6
| | | | | | | | +--------------- LC53 Q7
| | | | | | | | | +------------- LC54 ~545~1
| | | | | | | | | | +----------- LC61 ~551~1
| | | | | | | | | | | +--------- LC63 ~560~1
| | | | | | | | | | | | +------- LC50 ~566~1
| | | | | | | | | | | | | +----- LC55 ~569~1
| | | | | | | | | | | | | | +--- LC57 ~575~1
| | | | | | | | | | | | | | | +- LC59 ~578~1
| | | | | | | | | | | | | | | |
| | | | | | | | | | | | | | | | Other LABs fed by signals
| | | | | | | | | | | | | | | | that feed LAB 'D'
LC | | | | | | | | | | | | | | | | | A B C D | Logic cells that feed LAB 'D':
LC58 -> - - - - - - - - * - - - - - - - | - - - * | <-- |LPM_ADD_SUB:632|addcore:adder|g2cp2
LC56 -> - - - - * - - - - - - - - - - - | - - - * | <-- |LPM_ADD_SUB:632|addcore:adder|ps3
LC62 -> - - - - - * * * * - - - - - - - | - - - * | <-- |LPM_ADD_SUB:632|addcore:adder|ps4
LC60 -> * - - - - - - * * - - - - - - - | - - - * | <-- |LPM_ADD_SUB:632|datab_node6
LC54 -> - - - - - - - * - - * - - - - - | - - - * | <-- ~545~1
LC61 -> - - - - - - - - - * - - - - - - | - - - * | <-- ~551~1
LC50 -> - - * - - * - - - - - - - * - - | - - - * | <-- ~566~1
LC55 -> - - - - - - - - - - - - * - - - | - - - * | <-- ~569~1
LC57 -> - * - - * * - - - - - - - - - * | - - - * | <-- ~575~1
LC59 -> - - - - - - - - - - - - - - * - | - - - * | <-- ~578~1
Pin
9 -> - - - - - - * * * - - - - - * - | - * * * | <-- X0
11 -> * - - - - - * * - - - - * - - - | * * - * | <-- X1
19 -> * - - - - - - * - - - - - - - - | * * * * | <-- X2
6 -> * - - * - - - - - * - - - - - - | - - * * | <-- X3
20 -> * * * * * * * * * * * * * * * * | * - - * | <-- Y3
LC27 -> - * - - * * * * * - - - - - - - | - - - * | <-- |LPM_ADD_SUB:624|addcore:adder|addcore:adder0|result_node3
LC48 -> * - * - - * * * - - - - - - - - | - - - * | <-- |LPM_ADD_SUB:624|addcore:adder|addcore:adder0|result_node4
LC47 -> * - - - - - * * * - - - - - - - | - - - * | <-- |LPM_ADD_SUB:624|addcore:adder|addcore:adder0|result_node5
LC46 -> * - - - - - - * * - - - - - - - | - - - * | <-- |LPM_ADD_SUB:624|addcore:adder|addcore:adder0|result_node6
LC4 -> * - - - - - * * * - - - - - - - | - - - * | <-- |LPM_ADD_SUB:632|datab_node5
LC14 -> - - - - - - * - - - - * - - - - | - - - * | <-- ~557~1
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: e:\ajun\mult4x4.rpt
mult4x4
** EQUATIONS **
X0 : INPUT;
X1 : INPUT;
X2 : INPUT;
X3 : INPUT;
Y0 : INPUT;
Y1 : INPUT;
Y2 : INPUT;
Y3 : INPUT;
-- Node name is 'Q0' = '~251~1'
-- Equation name is 'Q0', location is LC033, type is output.
Q0 = LCELL( _EQ001 $ GND);
_EQ001 = X0 & Y0;
-- Node name is 'Q1'
-- Equation name is 'Q1', location is LC017, type is output.
Q1 = LCELL( _EQ002 $ GND);
_EQ002 = _X001 & _X002;
_X001 = EXP( _LC022 & _LC036);
_X002 = EXP(!_LC022 & !_LC036);
-- Node name is 'Q2'
-- Equation name is 'Q2', location is LC030, type is output.
Q2 = LCELL( _EQ003 $ GND);
_EQ003 = _X003 & _X004;
_X003 = EXP( _LC020 & _LC028 & Y2);
_X004 = EXP(!_LC028 & !_LC044);
-- Node name is 'Q3'
-- Equation name is 'Q3', location is LC052, type is output.
Q3 = LCELL( _EQ004 $ GND);
_EQ004 = !_LC056 & _X005;
_X005 = EXP( _LC027 & _LC057 & Y3);
-- Node name is 'Q4'
-- Equation name is 'Q4', location is LC051, type is output.
Q4 = LCELL( _EQ005 $ _EQ006);
_EQ005 = !_LC062 & _X006;
_X006 = EXP( _LC048 & _LC050 & Y3);
_EQ006 = _LC027 & _LC057 & Y3;
-- Node name is 'Q5'
-- Equation name is 'Q5', location is LC049, type is output.
Q5 = LCELL( _EQ007 $ _EQ008);
_EQ007 = _LC027 & !_LC062 & X0 & Y3
# _LC048 & X1 & Y3;
_EQ008 = _X007 & _X008;
_X007 = EXP( _LC014 & _LC047 & Y3);
_X008 = EXP(!_LC004 & !_LC047);
-- Node name is 'Q6'
-- Equation name is 'Q6', location is LC064, type is output.
Q6 = LCELL( _EQ009 $ _EQ010);
_EQ009 = _LC027 & !_LC062 & X0 & _X008 & Y3
# _LC048 & X1 & _X008 & Y3
# _LC047 & X2 & Y3;
_X008 = EXP(!_LC004 & !_LC047);
_EQ010 = _X009 & _X010;
_X009 = EXP( _LC046 & _LC054 & Y3);
_X010 = EXP(!_LC046 & !_LC060);
-- Node name is 'Q7'
-- Equation name is 'Q7', location is LC053, type is output.
Q7 = LCELL( _EQ011 $ _LC058);
_EQ011 = _LC027 & !_LC058 & !_LC062 & X0 & _X008 & _X010 & Y3;
_X008 = EXP(!_LC004 & !_LC047);
_X010 = EXP(!_LC046 & !_LC060);
-- Node name is '|LPM_ADD_SUB:617|addcore:adder|addcore:adder0|gc2~1' from file "addcore.tdf" line 361, column 19
-- Equation name is '_LC025', type is buried
-- synthesized logic cell
_LC025 = LCELL( _EQ012 $ GND);
_EQ012 = _LC022 & _LC036 & _X011
# _LC002 & _LC023;
_X011 = EXP(!_LC002 & !_LC023);
-- Node name is '|LPM_ADD_SUB:617|addcore:adder|addcore:adder0|g4' from file "addcore.tdf" line 158, column 5
-- Equation name is '_LC029', type is buried
_LC029 = LCELL( _EQ013 $ _LC038);
_EQ013 = _LC003 & _LC022 & _LC036 & !_LC038 & _X011
# _LC002 & _LC003 & _LC023 & !_LC038
# !_LC003 & !_LC025 & _LC038;
_X011 = EXP(!_LC002 & !_LC023);
-- Node name is '|LPM_ADD_SUB:617|addcore:adder|addcore:adder0|result_node2' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC028', type is buried
_LC028 = LCELL( _EQ014 $ _EQ015);
_EQ014 = _LC022 & _LC036;
_EQ015 = _X011 & _X012;
_X011 = EXP(!_LC002 & !_LC023);
_X012 = EXP( _LC002 & _LC023);
-- Node name is '|LPM_ADD_SUB:617|addcore:adder|addcore:adder0|result_node3' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC026', type is buried
_LC026 = LCELL( _EQ016 $ _LC025);
_EQ016 = _X013 & _X014;
_X013 = EXP(!_LC003 & !_LC038);
_X014 = EXP( _LC003 & _LC038);
-- Node name is '|LPM_ADD_SUB:617|addcore:adder|addcore:adder0|result_node4' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC045', type is buried
_LC045 = LCELL( _EQ017 $ _LC029);
_EQ017 = X3 & Y1;
-- Node name is '|LPM_ADD_SUB:624|addcore:adder|addcore:adder0|g2cp1' from file "addcore.tdf" line 159, column 9
-- Equation name is '_LC040', type is buried
_LC040 = LCELL( _EQ018 $ GND);
_EQ018 = _LC029 & X3 & Y1 & Y2
# !_LC037 & _LC045 & X2 & Y2;
-- Node name is '|LPM_ADD_SUB:624|addcore:adder|addcore:adder0|g4' from file "addcore.tdf" line 158, column 5
-- Equation name is '_LC024', type is buried
_LC024 = LCELL( _EQ019 $ _EQ020);
_EQ019 = _LC028 & !_LC031 & X0 & _X015 & Y2;
_X015 = EXP( _LC026 & X1 & Y2);
_EQ020 = _LC026 & _LC032 & Y2;
-- Node name is '|LPM_ADD_SUB:624|addcore:adder|addcore:adder0|ps3' from file "addcore.tdf" line 150, column 7
-- Equation name is '_LC031', type is buried
_LC031 = LCELL( _EQ021 $ GND);
_EQ021 = !_LC026 & _X016;
_X016 = EXP( _LC032 & Y2);
-- Node name is '|LPM_ADD_SUB:624|addcore:adder|addcore:adder0|ps5' from file "addcore.tdf" line 150, column 7
-- Equation name is '_LC037', type is buried
_LC037 = LCELL( _EQ022 $ _EQ023);
_EQ022 = _LC029 & X3 & _X017 & Y1;
_X017 = EXP( X3 & Y2);
_EQ023 = _X018;
_X018 = EXP( _LC035 & Y2);
-- Node name is '|LPM_ADD_SUB:624|addcore:adder|addcore:adder0|result_node3' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC027', type is buried
_LC027 = LCELL( _EQ024 $ _EQ025);
_EQ024 = !_LC031 & _X019;
_X019 = EXP( _LC026 & _LC032 & Y2);
_EQ025 = _LC028 & X0 & Y2;
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