📄 final.rpt
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| | +------- LC86 Y11
| | | +----- LC88 Y12
| | | | +--- LC85 Y13
| | | | | +- LC83 Y14
| | | | | |
| | | | | | Other LABs fed by signals
| | | | | | that feed LAB 'F'
LC | | | | | | | A B C D E F G H | Logic cells that feed LAB 'F':
Pin
83 -> - - - - - - | * - - - - - - - | <-- DATA0
84 -> - - - - - - | * - * - - - - - | <-- DATA1
1 -> - - - - - - | - - * - - - - * | <-- DATA2
LC50 -> - * * * * * | - - - - * * - - | <-- |mult5x5:1|MULT4X4:2|LPM_ADD_SUB:632|addcore:adder|result_node4
LC54 -> - * * * * * | - - - - * * - - | <-- |mult5x5:1|MULT4X4:2|LPM_ADD_SUB:632|addcore:adder|result_node5
LC58 -> - * * * * * | - - - - * * - - | <-- |mult5x5:1|MULT4X4:2|LPM_ADD_SUB:632|addcore:adder|result_node6
LC53 -> - * * * * * | - - - - * * - - | <-- |mult5x5:1|MULT4X4:2|LPM_ADD_SUB:632|addcore:adder|result_node7
LC1 -> * - - - - - | * - - - - * * - | <-- |mult5x5:1|PUTIN:1|~155~1
LC4 -> * - - - - - | * - - - - * * - | <-- |mult5x5:1|PUTIN:1|~200~1
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: d:\ajun\final.rpt
final
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'G':
Logic cells placed in LAB 'G'
+----------- LC105 S0
| +--------- LC104 S1
| | +------- LC107 S2
| | | +----- LC99 S3
| | | | +--- LC101 S4
| | | | | +- LC97 S6
| | | | | |
| | | | | | Other LABs fed by signals
| | | | | | that feed LAB 'G'
LC | | | | | | | A B C D E F G H | Logic cells that feed LAB 'G':
Pin
83 -> - - - - - - | * - - - - - - - | <-- DATA0
84 -> - - - - - - | * - * - - - - - | <-- DATA1
1 -> - - - - - - | - - * - - - - * | <-- DATA2
LC1 -> * * * * * * | * - - - - * * - | <-- |mult5x5:1|PUTIN:1|~155~1
LC4 -> * * * * * * | * - - - - * * - | <-- |mult5x5:1|PUTIN:1|~200~1
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: d:\ajun\final.rpt
final
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'H':
Logic cells placed in LAB 'H'
+- LC128 LED2
|
| Other LABs fed by signals
| that feed LAB 'H'
LC | | A B C D E F G H | Logic cells that feed LAB 'H':
Pin
83 -> - | * - - - - - - - | <-- DATA0
84 -> - | * - * - - - - - | <-- DATA1
1 -> * | - - * - - - - * | <-- DATA2
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: d:\ajun\final.rpt
final
** EQUATIONS **
CP0 : INPUT;
CP1 : INPUT;
DATA0 : INPUT;
DATA1 : INPUT;
DATA2 : INPUT;
DATA3 : INPUT;
DATA4 : INPUT;
-- Node name is 'LED0'
-- Equation name is 'LED0', location is LC014, type is output.
LED0 = LCELL(!DATA0 $ GND);
-- Node name is 'LED1'
-- Equation name is 'LED1', location is LC013, type is output.
LED1 = LCELL(!DATA1 $ GND);
-- Node name is 'LED2'
-- Equation name is 'LED2', location is LC128, type is output.
LED2 = LCELL(!DATA2 $ GND);
-- Node name is 'LED3'
-- Equation name is 'LED3', location is LC011, type is output.
LED3 = LCELL(!DATA3 $ GND);
-- Node name is 'LED4'
-- Equation name is 'LED4', location is LC005, type is output.
LED4 = LCELL(!DATA4 $ GND);
-- Node name is 'S0'
-- Equation name is 'S0', location is LC105, type is output.
S0 = LCELL( _LC004 $ !_LC001);
-- Node name is 'S1'
-- Equation name is 'S1', location is LC104, type is output.
S1 = _LC104~NOT;
_LC104~NOT = LCELL(!_LC004 $ !_LC001);
-- Node name is 'S2'
-- Equation name is 'S2', location is LC107, type is output.
S2 = _LC107~NOT;
_LC107~NOT = LCELL(!_LC004 $ !_LC001);
-- Node name is 'S3'
-- Equation name is 'S3', location is LC099, type is output.
S3 = _LC099~NOT;
_LC099~NOT = LCELL(!_LC004 $ !_LC001);
-- Node name is 'S4'
-- Equation name is 'S4', location is LC101, type is output.
S4 = _LC101~NOT;
_LC101~NOT = LCELL(!_LC004 $ !_LC001);
-- Node name is 'S5'
-- Equation name is 'S5', location is LC094, type is output.
S5 = _LC094~NOT;
_LC094~NOT = LCELL(!_LC004 $ !_LC001);
-- Node name is 'S6'
-- Equation name is 'S6', location is LC097, type is output.
S6 = _LC097~NOT;
_LC097~NOT = LCELL(!_LC004 $ !_LC001);
-- Node name is 'Y00'
-- Equation name is 'Y00', location is LC073, type is output.
Y00 = LCELL( _EQ001 $ GND);
_EQ001 = _LC010 & !_LC078 & _X001 & _X002 & _X003 & _X004
# !_LC010 & !_LC061 & !_LC074 & _X003 & _X004 & _X005
# !_LC062 & !_LC070 & !_LC078;
_X001 = EXP( _LC025 & _LC026);
_X002 = EXP(!_LC025 & !_LC026);
_X003 = EXP(!_LC068 & !_LC076);
_X004 = EXP( _LC033 & _LC068 & _LC071);
_X005 = EXP( _LC009 & _LC019 & _LC027);
-- Node name is 'Y01'
-- Equation name is 'Y01', location is LC069, type is output.
Y01 = LCELL( _EQ002 $ !_LC078);
_EQ002 = _LC010 & !_LC061 & !_LC074 & _X003 & _X004 & _X005
# !_LC074 & !_LC078 & _X003 & _X004
# !_LC010 & !_LC078 & _X003 & _X004
# !_LC010 & !_LC070 & !_LC078;
_X003 = EXP(!_LC068 & !_LC076);
_X004 = EXP( _LC033 & _LC068 & _LC071);
_X005 = EXP( _LC009 & _LC019 & _LC027);
-- Node name is 'Y02'
-- Equation name is 'Y02', location is LC072, type is output.
Y02 = LCELL( _EQ003 $ !_LC078);
_EQ003 = _LC010 & !_LC061 & !_LC062 & !_LC074 & _X005
# !_LC010 & !_LC078 & _X001 & _X002
# !_LC010 & !_LC062 & !_LC078;
_X005 = EXP( _LC009 & _LC019 & _LC027);
_X001 = EXP( _LC025 & _LC026);
_X002 = EXP(!_LC025 & !_LC026);
-- Node name is 'Y03'
-- Equation name is 'Y03', location is LC067, type is output.
Y03 = LCELL( _EQ004 $ GND);
_EQ004 = !_LC010 & !_LC061 & !_LC063 & _X001 & _X002 & _X005
# _LC010 & _X001 & _X002 & _X003 & _X004
# !_LC010 & !_LC074 & !_LC078 & _X003 & _X004
# _LC010 & !_LC062 & !_LC070 & !_LC078;
_X001 = EXP( _LC025 & _LC026);
_X002 = EXP(!_LC025 & !_LC026);
_X005 = EXP( _LC009 & _LC019 & _LC027);
_X003 = EXP(!_LC068 & !_LC076);
_X004 = EXP( _LC033 & _LC068 & _LC071);
-- Node name is 'Y04'
-- Equation name is 'Y04', location is LC065, type is output.
Y04 = LCELL( _EQ005 $ _EQ006);
_EQ005 = !_LC010 & !_LC063 & !_LC078 & _X001 & _X002
# _LC010 & !_LC061 & !_LC070 & _X005
# !_LC061 & !_LC062 & _X005;
_X001 = EXP( _LC025 & _LC026);
_X002 = EXP(!_LC025 & !_LC026);
_X005 = EXP( _LC009 & _LC019 & _LC027);
_EQ006 = !_LC061 & _X005;
_X005 = EXP( _LC009 & _LC019 & _LC027);
-- Node name is 'Y05'
-- Equation name is 'Y05', location is LC051, type is output.
Y05 = LCELL( _EQ007 $ _EQ008);
_EQ007 = !_LC010 & !_LC078 & _X001 & _X002 & _X003 & _X004
# _LC010 & !_LC074 & !_LC078 & _X003 & _X004
# _LC010 & !_LC061 & !_LC070 & _X005
# !_LC010 & !_LC061 & !_LC062 & _X005;
_X001 = EXP( _LC025 & _LC026);
_X002 = EXP(!_LC025 & !_LC026);
_X003 = EXP(!_LC068 & !_LC076);
_X004 = EXP( _LC033 & _LC068 & _LC071);
_X005 = EXP( _LC009 & _LC019 & _LC027);
_EQ008 = !_LC061 & _X005;
_X005 = EXP( _LC009 & _LC019 & _LC027);
-- Node name is 'Y06'
-- Equation name is 'Y06', location is LC049, type is output.
Y06 = LCELL( _EQ009 $ GND);
_EQ009 = _LC010 & !_LC061 & !_LC074 & _X003 & _X004 & _X005
# _LC010 & !_LC061 & !_LC063 & _X001 & _X002 & _X005
# !_LC010 & !_LC074 & !_LC078 & _X003 & _X004
# _LC010 & !_LC062 & !_LC070 & !_LC078;
_X003 = EXP(!_LC068 & !_LC076);
_X004 = EXP( _LC033 & _LC068 & _LC071);
_X005 = EXP( _LC009 & _LC019 & _LC027);
_X001 = EXP( _LC025 & _LC026);
_X002 = EXP(!_LC025 & !_LC026);
-- Node name is 'Y10'
-- Equation name is 'Y10', location is LC091, type is output.
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