📄 final.rpt
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final
** INPUTS **
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Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
33 (64) (D) INPUT 0 0 0 0 0 0 10 CP0
34 (61) (D) INPUT 0 0 0 0 0 0 5 CP1
83 - - INPUT 0 0 0 0 0 1 2 DATA0
84 - - INPUT 0 0 0 0 0 1 2 DATA1
1 - - INPUT 0 0 0 0 0 1 2 DATA2
37 (56) (D) INPUT 0 0 0 0 0 1 2 DATA3
36 (57) (D) INPUT 0 0 0 0 0 1 2 DATA4
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: d:\ajun\final.rpt
final
** OUTPUTS **
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Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
5 14 A OUTPUT t 0 0 0 1 0 0 0 LED0
6 13 A OUTPUT t 0 0 0 1 0 0 0 LED1
81 128 H OUTPUT t 0 0 0 1 0 0 0 LED2
8 11 A OUTPUT t 0 0 0 1 0 0 0 LED3
11 5 A OUTPUT t 0 0 0 1 0 0 0 LED4
68 105 G OUTPUT t 0 0 0 0 2 0 0 S0
67 104 G OUTPUT t ! 0 0 0 0 2 0 0 S1
69 107 G OUTPUT t ! 0 0 0 0 2 0 0 S2
64 99 G OUTPUT t ! 0 0 0 0 2 0 0 S3
65 101 G OUTPUT t ! 0 0 0 0 2 0 0 S4
61 94 F OUTPUT t ! 0 0 0 0 2 0 0 S5
63 97 G OUTPUT t ! 0 0 0 0 2 0 0 S6
49 73 E OUTPUT t 5 5 0 0 15 0 0 Y00
46 69 E OUTPUT t 4 3 1 0 12 0 0 Y01
48 72 E OUTPUT t 3 3 0 0 10 0 0 Y02
45 67 E OUTPUT t 5 5 0 0 16 0 0 Y03
44 65 E OUTPUT t 3 3 0 0 11 0 0 Y04
40 51 D OUTPUT t 6 5 1 0 15 0 0 Y05
41 49 D OUTPUT t 5 5 0 0 16 0 0 Y06
58 91 F OUTPUT t 0 0 0 0 4 0 0 Y10
56 86 F OUTPUT t 1 0 1 0 4 0 0 Y11
57 88 F OUTPUT t 0 0 0 0 4 0 0 Y12
55 85 F OUTPUT t 0 0 0 0 4 0 0 Y13
54 83 F OUTPUT t 0 0 0 0 4 0 0 Y14
50 75 E OUTPUT t 1 0 1 0 4 0 0 Y15
52 80 E OUTPUT t 0 0 0 0 4 0 0 Y16
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: d:\ajun\final.rpt
final
** BURIED LOGIC **
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Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
- 66 E SOFT s t 1 1 0 0 4 0 2 |mult5x5:1|MULT4X4:2|LPM_ADD_SUB:617|addcore:adder|addcore:adder0|gc2~1
(51) 77 E SOFT t 1 1 0 0 7 0 4 |mult5x5:1|MULT4X4:2|LPM_ADD_SUB:617|addcore:adder|addcore:adder0|g4
- 70 E SOFT t 2 2 0 0 2 6 0 |mult5x5:1|MULT4X4:2|LPM_ADD_SUB:617|addcore:adder|addcore:adder0|result_node1
- 68 E SOFT t 2 1 0 0 4 5 4 |mult5x5:1|MULT4X4:2|LPM_ADD_SUB:617|addcore:adder|addcore:adder0|result_node2
- 79 E SOFT t 2 0 0 0 3 0 3 |mult5x5:1|MULT4X4:2|LPM_ADD_SUB:617|addcore:adder|addcore:adder0|result_node3
(30) 37 C SOFT t 0 0 0 0 3 0 4 |mult5x5:1|MULT4X4:2|LPM_ADD_SUB:617|addcore:adder|addcore:adder0|result_node4
(27) 43 C SOFT t 0 0 0 0 7 0 1 |mult5x5:1|MULT4X4:2|LPM_ADD_SUB:624|addcore:adder|addcore:adder0|g2cp1
(22) 17 B SOFT t 1 1 0 0 6 0 3 |mult5x5:1|MULT4X4:2|LPM_ADD_SUB:624|addcore:adder|addcore:adder0|g4
(14) 32 B SOFT t 1 0 0 0 3 0 2 |mult5x5:1|MULT4X4:2|LPM_ADD_SUB:624|addcore:adder|addcore:adder0|ps3
- 36 C SOFT t 2 0 0 0 5 0 3 |mult5x5:1|MULT4X4:2|LPM_ADD_SUB:624|addcore:adder|addcore:adder0|ps5
- 62 D SOFT t 2 2 0 0 4 6 0 |mult5x5:1|MULT4X4:2|LPM_ADD_SUB:624|addcore:adder|addcore:adder0|result_node2
(21) 19 B SOFT t 1 1 0 0 6 7 6 |mult5x5:1|MULT4X4:2|LPM_ADD_SUB:624|addcore:adder|addcore:adder0|result_node3
(31) 35 C SOFT t 2 1 0 0 5 0 5 |mult5x5:1|MULT4X4:2|LPM_ADD_SUB:624|addcore:adder|addcore:adder0|result_node4
- 42 C SOFT t 2 1 0 0 10 0 4 |mult5x5:1|MULT4X4:2|LPM_ADD_SUB:624|addcore:adder|addcore:adder0|result_node5
(25) 45 C SOFT t 1 1 0 0 5 0 3 |mult5x5:1|MULT4X4:2|LPM_ADD_SUB:624|addcore:adder|addcore:adder0|result_node6
- 76 E SOFT t 0 0 0 0 2 5 2 |mult5x5:1|MULT4X4:2|LPM_ADD_SUB:624|datab_node2
- 47 C SOFT t 0 0 0 0 2 0 3 |mult5x5:1|MULT4X4:2|LPM_ADD_SUB:624|datab_node4
- 55 D SOFT t 1 1 0 0 9 0 1 |mult5x5:1|MULT4X4:2|LPM_ADD_SUB:632|addcore:adder|g2cp2
(34) 61 D SOFT t 1 0 0 0 3 7 1 |mult5x5:1|MULT4X4:2|LPM_ADD_SUB:632|addcore:adder|ps3
- 60 D SOFT t 1 0 0 0 3 0 4 |mult5x5:1|MULT4X4:2|LPM_ADD_SUB:632|addcore:adder|ps4
(37) 56 D SOFT t 1 0 0 0 3 0 4 |mult5x5:1|MULT4X4:2|LPM_ADD_SUB:632|addcore:adder|ps5
- 74 E SOFT t 2 2 0 0 2 6 0 |mult5x5:1|MULT4X4:2|LPM_ADD_SUB:632|addcore:adder|result_node1
- 63 D SOFT t 2 2 0 0 4 3 0 |mult5x5:1|MULT4X4:2|LPM_ADD_SUB:632|addcore:adder|result_node2
- 78 E SOFT t 1 1 0 0 4 7 0 |mult5x5:1|MULT4X4:2|LPM_ADD_SUB:632|addcore:adder|result_node3
- 50 D SOFT t 1 0 0 0 6 7 0 |mult5x5:1|MULT4X4:2|LPM_ADD_SUB:632|addcore:adder|result_node4
- 54 D SOFT t 1 0 0 0 9 7 0 |mult5x5:1|MULT4X4:2|LPM_ADD_SUB:632|addcore:adder|result_node5
- 58 D SOFT t 2 1 0 0 12 7 0 |mult5x5:1|MULT4X4:2|LPM_ADD_SUB:632|addcore:adder|result_node6
(39) 53 D SOFT t 1 1 0 0 8 7 0 |mult5x5:1|MULT4X4:2|LPM_ADD_SUB:632|addcore:adder|result_node7
- 20 B SOFT t 0 0 0 0 2 0 3 |mult5x5:1|MULT4X4:2|LPM_ADD_SUB:632|datab_node6
(9) 8 A LCELL s t 0 0 0 0 2 0 2 |mult5x5:1|MULT4X4:2|~224~1
(10) 6 A LCELL s t 0 0 0 0 2 0 3 |mult5x5:1|MULT4X4:2|~233~1
(17) 25 B LCELL s t 0 0 0 0 2 6 5 |mult5x5:1|MULT4X4:2|~242~1
(18) 24 B SOFT s t 0 0 0 0 3 0 1 |mult5x5:1|MULT4X4:2|~248~1
- 10 A LCELL s t 0 0 0 0 2 7 1 |mult5x5:1|MULT4X4:2|~251~1
- 30 B SOFT s t 0 0 0 0 3 0 2 |mult5x5:1|MULT4X4:2|~312~1
- 41 C LCELL s t 0 0 0 0 2 0 1 |mult5x5:1|MULT4X4:2|~318~1
(23) 48 C LCELL s t 0 0 0 0 2 0 2 |mult5x5:1|MULT4X4:2|~327~1
(20) 21 B SOFT s t 0 0 0 0 3 0 1 |mult5x5:1|MULT4X4:2|~333~1
- 23 B LCELL s t 0 0 0 0 2 0 4 |mult5x5:1|MULT4X4:2|~336~1
- 26 B LCELL s t 0 0 0 0 2 6 5 |mult5x5:1|MULT4X4:2|~345~1
- 28 B SOFT s t 0 0 0 0 3 0 2 |mult5x5:1|MULT4X4:2|~421~1
(29) 38 C LCELL s t 0 0 0 0 2 0 1 |mult5x5:1|MULT4X4:2|~427~1
(28) 40 C SOFT s t 0 0 0 0 3 0 2 |mult5x5:1|MULT4X4:2|~433~1
- 39 C LCELL s t 0 0 0 0 2 0 1 |mult5x5:1|MULT4X4:2|~436~1
- 31 B SOFT s t 0 0 0 0 3 0 4 |mult5x5:1|MULT4X4:2|~442~1
(15) 29 B LCELL s t 0 0 0 0 2 0 1 |mult5x5:1|MULT4X4:2|~445~1
- 71 E SOFT s t 0 0 0 0 3 5 3 |mult5x5:1|MULT4X4:2|~451~1
(36) 57 D LCELL s t 0 0 0 0 2 0 1 |mult5x5:1|MULT4X4:2|~454~1
- 12 A SOFT s t 0 0 0 0 3 0 2 |mult5x5:1|MULT4X4:2|~545~1
(4) 16 A LCELL s t 0 0 0 0 2 0 1 |mult5x5:1|MULT4X4:2|~551~1
- 15 A SOFT s t 0 0 0 0 3 0 3 |mult5x5:1|MULT4X4:2|~557~1
(35) 59 D LCELL s t 0 0 0 0 2 0 1 |mult5x5:1|MULT4X4:2|~560~1
- 18 B SOFT s t 0 0 0 0 3 0 3 |mult5x5:1|MULT4X4:2|~566~1
(33) 64 D LCELL s t 0 0 0 0 2 0 1 |mult5x5:1|MULT4X4:2|~569~1
(16) 27 B SOFT s t 0 0 0 0 3 7 4 |mult5x5:1|MULT4X4:2|~575~1
- 52 D LCELL s t 0 0 0 0 2 0 1 |mult5x5:1|MULT4X4:2|~578~1
- 9 A LCELL s t 1 0 1 3 1 7 19 |mult5x5:1|PUTIN:1|~119~1
- 33 C LCELL s t 1 0 1 3 1 5 20 |mult5x5:1|PUTIN:1|~128~1
- 34 C LCELL s t 1 0 1 3 1 0 11 |mult5x5:1|PUTIN:1|~137~1
- 7 A LCELL s t 1 0 1 3 1 0 6 |mult5x5:1|PUTIN:1|~146~1
- 1 A LCELL s t 1 0 1 3 1 7 1 |mult5x5:1|PUTIN:1|~155~1
(12) 3 A LCELL s t 0 0 0 2 1 0 11 |mult5x5:1|PUTIN:1|~164~1
- 44 C LCELL s t 0 0 0 2 1 0 10 |mult5x5:1|PUTIN:1|~173~1
(24) 46 C LCELL s t 0 0 0 2 1 0 8 |mult5x5:1|PUTIN:1|~182~1
- 2 A LCELL s t 0 0 0 2 1 0 11 |mult5x5:1|PUTIN:1|~191~1
- 4 A LCELL s t 0 0 0 2 1 7 1 |mult5x5:1|PUTIN:1|~200~1
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: d:\ajun\final.rpt
final
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'A':
Logic cells placed in LAB 'A'
+------------------------------- LC14 LED0
| +----------------------------- LC13 LED1
| | +--------------------------- LC11 LED3
| | | +------------------------- LC5 LED4
| | | | +----------------------- LC8 |mult5x5:1|MULT4X4:2|~224~1
| | | | | +--------------------- LC6 |mult5x5:1|MULT4X4:2|~233~1
| | | | | | +------------------- LC10 |mult5x5:1|MULT4X4:2|~251~1
| | | | | | | +----------------- LC12 |mult5x5:1|MULT4X4:2|~545~1
| | | | | | | | +--------------- LC16 |mult5x5:1|MULT4X4:2|~551~1
| | | | | | | | | +------------- LC15 |mult5x5:1|MULT4X4:2|~557~1
| | | | | | | | | | +----------- LC9 |mult5x5:1|PUTIN:1|~119~1
| | | | | | | | | | | +--------- LC7 |mult5x5:1|PUTIN:1|~146~1
| | | | | | | | | | | | +------- LC1 |mult5x5:1|PUTIN:1|~155~1
| | | | | | | | | | | | | +----- LC3 |mult5x5:1|PUTIN:1|~164~1
| | | | | | | | | | | | | | +--- LC2 |mult5x5:1|PUTIN:1|~191~1
| | | | | | | | | | | | | | | +- LC4 |mult5x5:1|PUTIN:1|~200~1
| | | | | | | | | | | | | | | |
| | | | | | | | | | | | | | | | Other LABs fed by signals
| | | | | | | | | | | | | | | | that feed LAB 'A'
LC | | | | | | | | | | | | | | | | | A B C D E F G H | Logic cells that feed LAB 'A':
LC12 -> - - - - - - - - * - - - - - - - | * - - * - - - - | <-- |mult5x5:1|MULT4X4:2|~545~1
LC16 -> - - - - - - - * - - - - - - - - | * - - - - - - - | <-- |mult5x5:1|MULT4X4:2|~551~1
LC9 -> - - - - - - - * * * * - - - - - | * * - * * - - - | <-- |mult5x5:1|PUTIN:1|~119~1
LC7 -> - - - - * * * - - - - * - - - - | * * - - - - - - | <-- |mult5x5:1|PUTIN:1|~146~1
LC1 -> - - - - - - - - - - - - * - - - | * - - - - * * - | <-- |mult5x5:1|PUTIN:1|~155~1
LC3 -> - - - - * - - * - - - - - * - - | * * * * - - - - | <-- |mult5x5:1|PUTIN:1|~164~1
LC2 -> - - - - - - - - - - - - - - * - | * * - * * - - - | <-- |mult5x5:1|PUTIN:1|~191~1
LC4 -> - - - - - - - - - - - - - - - * | * - - - - * * - | <-- |mult5x5:1|PUTIN:1|~200~1
Pin
33 -> - - - - - - - - - - * * * * * * | * - * - - - - - | <-- CP0
34 -> - - - - - - - - - - * * * - - - | * - * - - - - - | <-- CP1
83 -> * - - - - - - - - - - * - - * - | * - - - - - - - | <-- DATA0
84 -> - * - - - - - - - - - - - - - - | * - * - - - - - | <-- DATA1
1 -> - - - - - - - - - - - - - - - - | - - * - - - - * | <-- DATA2
37 -> - - * - - - - - - - * - - * - - | * - - - - - - - | <-- DATA3
36 -> - - - * - - - - - - - - * - - * | * - - - - - - - | <-- DATA4
LC24 -> - - - - - - * - - - - - - - - - | * - - - - - - - | <-- |mult5x5:1|MULT4X4:2|~248~1
LC59 -> - - - - - - - - - * - - - - - - | * - - - - - - - | <-- |mult5x5:1|MULT4X4:2|~560~1
LC44 -> - - - - - * - - - * - - - - - - | * - * * - - - - | <-- |mult5x5:1|PUTIN:1|~173~1
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: d:\ajun\final.rpt
final
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'B':
Logic cells placed in LAB 'B'
+----------------------------- LC17 |mult5x5:1|MULT4X4:2|LPM_ADD_SUB:624|addcore:adder|addcore:adder0|g4
| +--------------------------- LC32 |mult5x5:1|MULT4X4:2|LPM_ADD_SUB:624|addcore:adder|addcore:adder0|ps3
| | +------------------------- LC19 |mult5x5:1|MULT4X4:2|LPM_ADD_SUB:624|addcore:adder|addcore:adder0|result_node3
| | | +----------------------- LC20 |mult5x5:1|MULT4X4:2|LPM_ADD_SUB:632|datab_node6
| | | | +--------------------- LC25 |mult5x5:1|MULT4X4:2|~242~1
| | | | | +------------------- LC24 |mult5x5:1|MULT4X4:2|~248~1
| | | | | | +----------------- LC30 |mult5x5:1|MULT4X4:2|~312~1
| | | | | | | +--------------- LC21 |mult5x5:1|MULT4X4:2|~333~1
| | | | | | | | +------------- LC23 |mult5x5:1|MULT4X4:2|~336~1
| | | | | | | | | +----------- LC26 |mult5x5:1|MULT4X4:2|~345~1
| | | | | | | | | | +--------- LC28 |mult5x5:1|MULT4X4:2|~421~1
| | | | | | | | | | | +------- LC31 |mult5x5:1|MULT4X4:2|~442~1
| | | | | | | | | | | | +----- LC29 |mult5x5:1|MULT4X4:2|~445~1
| | | | | | | | | | | | | +--- LC18 |mult5x5:1|MULT4X4:2|~566~1
| | | | | | | | | | | | | | +- LC27 |mult5x5:1|MULT4X4:2|~575~1
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