📄 monitor.rpt
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* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: e:\ajun\monitor.rpt
monitor
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'H':
Logic cells placed in LAB 'H'
+------------- LC118 Y00
| +----------- LC115 Y01
| | +--------- LC120 Y02
| | | +------- LC117 Y03
| | | | +----- LC123 Y04
| | | | | +--- LC125 Y05
| | | | | | +- LC126 Y06
| | | | | | |
| | | | | | | Other LABs fed by signals
| | | | | | | that feed LAB 'H'
LC | | | | | | | | A B C D E F G H | Logic cells that feed LAB 'H':
Pin
12 -> * * * * * * * | - - - - - - - * | <-- A0
4 -> * * * * * * * | - - - - - - - * | <-- A1
5 -> * * * * * * * | - - - - - - - * | <-- A2
6 -> * * * * * * * | - - - - - - - * | <-- A3
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: e:\ajun\monitor.rpt
monitor
** EQUATIONS **
A0 : INPUT;
A1 : INPUT;
A2 : INPUT;
A3 : INPUT;
A4 : INPUT;
A5 : INPUT;
A6 : INPUT;
A7 : INPUT;
SIGN : INPUT;
-- Node name is 'S0'
-- Equation name is 'S0', location is LC094, type is output.
S0 = LCELL(!SIGN $ GND);
-- Node name is 'S1'
-- Equation name is 'S1', location is LC091, type is output.
S1 = LCELL(!SIGN $ VCC);
-- Node name is 'S2'
-- Equation name is 'S2', location is LC086, type is output.
S2 = LCELL(!SIGN $ VCC);
-- Node name is 'S3'
-- Equation name is 'S3', location is LC083, type is output.
S3 = LCELL(!SIGN $ VCC);
-- Node name is 'S4'
-- Equation name is 'S4', location is LC085, type is output.
S4 = LCELL(!SIGN $ VCC);
-- Node name is 'S5'
-- Equation name is 'S5', location is LC088, type is output.
S5 = LCELL(!SIGN $ VCC);
-- Node name is 'S6'
-- Equation name is 'S6', location is LC093, type is output.
S6 = LCELL(!SIGN $ VCC);
-- Node name is 'Y00'
-- Equation name is 'Y00', location is LC118, type is output.
Y00 = LCELL( _EQ001 $ GND);
_EQ001 = A0 & A1 & A2 & !A3
# !A0 & !A1 & A2 & A3
# !A1 & !A2 & !A3;
-- Node name is 'Y01'
-- Equation name is 'Y01', location is LC115, type is output.
Y01 = LCELL( _EQ002 $ !A3);
_EQ002 = A0 & !A1 & A2 & A3
# !A1 & A2 & !A3
# !A0 & A2 & !A3
# !A0 & !A1 & !A3;
-- Node name is 'Y02'
-- Equation name is 'Y02', location is LC120, type is output.
Y02 = LCELL( _EQ003 $ !A3);
_EQ003 = A0 & !A1 & !A2 & A3
# !A0 & A1 & !A3
# !A0 & !A2 & !A3;
-- Node name is 'Y03'
-- Equation name is 'Y03', location is LC117, type is output.
Y03 = LCELL( _EQ004 $ GND);
_EQ004 = !A0 & A1 & !A2 & A3
# A0 & !A1 & !A2 & !A3
# !A0 & !A1 & A2 & !A3
# A0 & A1 & A2;
-- Node name is 'Y04'
-- Equation name is 'Y04', location is LC123, type is output.
Y04 = LCELL( _EQ005 $ A3);
_EQ005 = !A0 & A1 & !A2 & !A3
# A0 & !A1 & A3
# !A2 & A3;
-- Node name is 'Y05'
-- Equation name is 'Y05', location is LC125, type is output.
Y05 = LCELL( _EQ006 $ A3);
_EQ006 = A0 & !A1 & A2 & !A3
# !A0 & A1 & A2 & !A3
# A0 & !A1 & A3
# !A0 & !A2 & A3;
-- Node name is 'Y06'
-- Equation name is 'Y06', location is LC126, type is output.
Y06 = LCELL( _EQ007 $ GND);
_EQ007 = A0 & !A1 & A2 & A3
# A0 & A1 & !A2 & A3
# !A0 & !A1 & A2 & !A3
# A0 & !A1 & !A2 & !A3;
-- Node name is 'Y10'
-- Equation name is 'Y10', location is LC097, type is output.
Y10 = LCELL( _EQ008 $ GND);
_EQ008 = A4 & A5 & A6 & !A7
# !A4 & !A5 & A6 & A7
# !A5 & !A6 & !A7;
-- Node name is 'Y11'
-- Equation name is 'Y11', location is LC109, type is output.
Y11 = LCELL( _EQ009 $ !A7);
_EQ009 = A4 & !A5 & A6 & A7
# !A5 & A6 & !A7
# !A4 & A6 & !A7
# !A4 & !A5 & !A7;
-- Node name is 'Y12'
-- Equation name is 'Y12', location is LC099, type is output.
Y12 = LCELL( _EQ010 $ !A7);
_EQ010 = A4 & !A5 & !A6 & A7
# !A4 & A5 & !A7
# !A4 & !A6 & !A7;
-- Node name is 'Y13'
-- Equation name is 'Y13', location is LC101, type is output.
Y13 = LCELL( _EQ011 $ GND);
_EQ011 = !A4 & A5 & !A6 & A7
# A4 & !A5 & !A6 & !A7
# !A4 & !A5 & A6 & !A7
# A4 & A5 & A6;
-- Node name is 'Y14'
-- Equation name is 'Y14', location is LC104, type is output.
Y14 = LCELL( _EQ012 $ A7);
_EQ012 = !A4 & A5 & !A6 & !A7
# A4 & !A5 & A7
# !A6 & A7;
-- Node name is 'Y15'
-- Equation name is 'Y15', location is LC105, type is output.
Y15 = LCELL( _EQ013 $ A7);
_EQ013 = A4 & !A5 & A6 & !A7
# !A4 & A5 & A6 & !A7
# A4 & !A5 & A7
# !A4 & !A6 & A7;
-- Node name is 'Y16'
-- Equation name is 'Y16', location is LC107, type is output.
Y16 = LCELL( _EQ014 $ GND);
_EQ014 = A4 & !A5 & A6 & A7
# A4 & A5 & !A6 & A7
# !A4 & !A5 & A6 & !A7
# A4 & !A5 & !A6 & !A7;
-- Shareable expanders that are duplicated in multiple LABs:
-- (none)
Project Information e:\ajun\monitor.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Standard
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'MAX7000S' family
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
PARALLEL_EXPANDERS = off
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SOFT_BUFFER_INSERTION = on
SUBFACTOR_EXTRACTION = on
TURBO_BIT = on
XOR_SYNTHESIS = on
IGNORE_SOFT_BUFFERS = off
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
One-Hot State Machine Encoding = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:00
Timing SNF Extractor 00:00:00
Assembler 00:00:01
-------------------------- --------
Total Time 00:00:01
Memory Allocated
-----------------
Peak memory allocated during compilation = 4,869K
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